Wyniki wyszukiwania - BazTech

1

Ultra-low Power FinFET SRAM Cell with Improved Stability Suitable for Low Power Applications

Birla Shilpi

International Journal of Electronics and Telecommunications

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2019

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Vol. 65, No. 4

603--609

EN

In this paper, a new 11T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power. The cell shows improvement in RSNM (Read Static Noise Margin) with LP8T by 2.39x at sub-threshold voltage 2.68x with D6T SRAM cell, 5.5x with TG8T. The WSNM (Write Static Noise Margin) and HM (Hold Margin) of the SRAM cell at 0.9V is 306mV and 384mV. At sub-threshold operation also it shows improvement. The Leakage power reduced by 0.125x with LP8T, 0.022x with D6T SRAM cell, TG8T and SE8T. Also, impact of process variation on cell stability is discussed.

2

Analysis of the Dispersion of Electrical Parameters and Characteristics of FinFET Devices

Malinowski A., Tomaszewski D., Łukasiak L., Jakubowski A., Sekine M., Hori M., Korwin-Pawlowski M. L.

Journal of Telecommunications and Information Technology

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2009

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nr 4

45-50

EN

Extensive numerical simulations of FinFET structures have been carried out using commercial TCAD tools. A series of plasma etching steps has been simulated for different process conditions in order to evaluate the influence of plasma pressure, composition and powering on the FinFET topography. Next, the most important geometric parameters of the FinFETs have been varied and the electrical characteristics have been calculated in order to evaluate the sensitivity of the FinFET electrical parameters on possible FinFET structure variability.

3

Opracowanie submikronowego tranzystora testowego typu FinFET

Zaborowski M., Kucharski K., Tomaszewski D., Panas A., Budzyński T., Grabiec P.

Elektronika : konstrukcje, technologie, zastosowania

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2008

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Vol. 49, nr 1

67-70

EN

A test 3-Gate FinFET-type p-MOS transistor was manufactured using a 3um CMOS layout and a technique dedicated for preparation of 270nm narrow silicon paths, controlled by means of a lateral definition process (PADEOX). SEM and optical views of the device were presented. I D (V DS) and I D (V GS) characteristics were measured and displayed together with typical p-MOS curves. A simple model of I-V characteristics was adopted for estimation of parameters of the fabricated test device.

PL

3-bramkowy tranzystor p-MOS typu Fin został opracowany przy wykorzystaniu 3 µm reguły projektowania (technologia CMOS) i nowej metody wytwarzania w procesie lateralnym wąskich ścieżek krzemowych o szerokości rzędu 270 nm (PADEOX). Zaprezentowano zdjęcia optyczne i skaningowe tranzystorów. Przedstawiono charakterystyki I D (V DS) i I D (V GS) w porównaniu z krzywymi typowymi dla technologii p-MOS. Wyznaczono podstawowe parametry elektryczne przyrządu i na ich podstawie charakterystyki I-V jego prostego modelu.

4

Charakteryzacja tranzystorów typu FinFET na podstawie analizy statycznych charakterystyk prądowo-napięciowych

Gibki J., Łukasiak L., Jakubowski A.

Elektronika : konstrukcje, technologie, zastosowania

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2008

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Vol. 49, nr 9

24-26

PL

W artykule przedstawiono wyniki pomiarów i identyfikacji podstawowych parametrów statycznych tranzystorów typu FinFET. Szczególną uwagę zwrócono na wielkości prądu drenu w stanie słabej inwersji i prądu upływności bramki ważnych z punktu widzenia wytwarzania szybkich i energooszczędnych układów scalonych.

EN

The paper presents the results of measurements and extraction of basic FinFET parameters. Special attention is paid to drain-to-source leakage current and gate leakage current, important from the point of view of fast, low-power integrated circuits fabrication.

5

Semiconductor cleaning technology for next generation material systems

Ruzyllo J.

Journal of Telecommunications and Information Technology

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2007

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nr 2

44-48

EN

This paper gives a brief overview of the challenges wafer cleaning technology is facing in the light of advanced silicon technology moving in the direction of non-planar device structures and the need for modified cleans for semiconductors other than silicon. In the former case, the key issue is related to cleaning and conditioning of vertical surfaces in next generation CMOS gate structure as well as deep 3D geometries in MEMS devices. In the latter, an accelerated pace at which semiconductors other than silicon are being introduced into the mainstream manufacturing calls for the development of material specific wafer cleaning technologies. Examples of the problems related to each challenge are considered.