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On implementation of FFT processor in XILINX FPGA using high-level synthesis

Smyk Robert, Czyżak Maciej

Poznan University of Technology Academic Journals. Electrical Engineering

2020

No. 104

17--33

The paper presents results of the high level synthesis of an 1024-point radix-2 FFT processors in Xilinx Vivado FPGA environment. The use of various directives controlling the synthesis process is examined. The results indicate that using the proper set of directives the latency of the processor can be reduced by 95% from about 35k for the default parameters to 1.5k cycles after optimizations.