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Instruction driven CPU in the FPGA structure

Gracki K., Pawłowski M., Skorupski A., Szymański Z.

Measurement Automation Monitoring

2016

Vol. 62, No. 5

169--171

The paper presents the design of processors embedded in an FPGA structure. The type of processor is determined by the preset instruction list. Each instruction is implemented as one functional block attached to a common bus. The processor contains two additional blocks: one contains a common register block and second is responsible for the fetch of the instruction from the program memory. To design the processor, one can choose the instruction set from the library of instructions components. The library is a set of VHDL descriptions of all possible instructions.

Automatic balancing of rotating systems: control algorithm's implementation on FPGA systems

Mańka M., Karpiel G., Uhl T.

Archives of Control Sciences

2007

Vol. 17, no. 3

329-342

The paper deals with automatic balancing of rotating systems during operation. After discussion of techniques' principles, balancing mechanisms designed on `AGH' University of Science and Technology are presented. After introduction into active balancing control algorithms, test results obtained during experiments are presented. The paper presents comparison between implementation process and results of experiments taken with two different control algorithms' implementation platforms: dSPACE rapid prototyping system and ALTERA FPGA system. The paper ends some conclusions about taken experiments and further works directions are presented.