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FPGA realization of the high-speed residue-to-binary converter based on the Chinese Remainder Theorem

Czyżak M., Smyk R.

Poznan University of Technology Academic Journals. Electrical Engineering

2010

No. 63

197-203

An architecture and the FPGA realization of a high-speed residue-to-binary converter for five-bit moduli are presented. The converter algorithm is based on the Chinese Remainder Theorem. The orthogonal projections are obtained by the look-up. The modulo M summation of projections is carried out by using the tree of carry-save adders with the succesive reduction of the sum to 2M range. Succesively the segmentation of the output vectors of the carry-save adder and final modulo M reduction are performed.