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Enhanced clock gating technique for power optimization in SRAM and sequential circuit

Ashok Kumar C., Madhavi B.K., Lal Kishore K.

Journal of Automation Mobile Robotics and Intelligent Systems

2021

Vol. 15, No. 2

32--38

Low power VLSI designs are having wide variety of application usage in real-time. VLSI circuits are analyzed with various power reduction strategies. Existing approaches are used the clock frequency control, switching activity and scaling factor for power reduction. The glitching problem and clock triggering issues are higher therefore; the proposed work utilized the improved circuit of clock gating technique. In this proposed work, the enhanced clock gating with D-latch model is constructed to obtain the less power consumption. The traditional clock gating technique is improved by adding clock triggering on LATCH circuit and adding buffer circuit between the source and load circuitry to reduce the clock switching issues like gitching and clocking activity. Here the SRAM and sequential counter circuits are designed to utilize the power reduction strategy for improving the performance. This is applicable for various applications in real world and utilizing the FPGA and DSP application specific circuits. Experimental results are analyzed to obtain the power reduction result of SRAM and sequential circuit. Area, power, and delay are obtained the better results as compared with the previous work. Overall, design is performed using Xilinx 14.2 ISE suit.

Performance Enhancement Heterogeneous Based EECP for Bandwidth Utilization

Kaur Gagandeep, Mishra Vinod Kumar

Annals of Computer Science and Information Systems

2017

Vol. 10

207--215

Using the increase of user made on distributed network scheme, traffic congestion is one of the necessary circumstances. Distributed network consists of various networks, processors and intermediary strategies that overwork the changes or routers with high traffic and it is because of the project fault in the circulated networking architecture. Even though several researchers address the congestion recognition method, its avoidance and modification in their investigation are solid to be explored for any effective solution for this problem. Due to huge network congestion user will face the network speed problem, real congestion control methods are desirable, and mainly to solve``bursty'' transportation of today's for actual extraordinary speed networks. Subsequently dawn 90's many systems have been proposed. This paper concentrates on heterogeneity based congestion mechanism patterns on the basis of certain key performance metrics. Mainly in this work we will judge the performance of Delay, congestion rate, throughput and channel capacity EECP based solution for a steady state against these key performance metrics.