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Enhancing approach using hybrid pailler and RSA for information security in bigdata

Abdalwahid Shadan Mohammed Jihad, Yousif Raghad Zuhair, Kareem Shahab Wahhab

Applied Computer Science

2019

Vol. 15, no 4

63--74

The amount of data processed and stored in the cloud is growing dramatically. The traditional storage devices at both hardware and software levels cannot meet the requirement of the cloud. This fact motivates the need for a platform which can handle this problem. Hadoop is a deployed platform proposed to overcome this big data problem which often uses MapReduce architecture to process vast amounts of data of the cloud system. Hadoop has no strategy to assure the safety and confidentiality of the files saved inside the Hadoop distributed File system (HDFS). In the cloud, the protection of sensitive data is a critical issue in which data encryption schemes plays avital rule. This research proposes a hybrid system between two well-known asymmetric key cryptosystems (RSA, and Paillier) to encrypt the files stored in HDFS. Thus before saving data in HDFS, the proposed cryptosystem is utilized for encrypting the data. Each user of the cloud might upload files in two ways, non-safe or secure. The hybrid system shows higher computational complexity and less latency in comparison to the RSA cryptosystem alone.

On-chip current-mode approach to thwart CPA attacks in CMOS nanometer technology

Bellizia D., Scotti G., Trifiletti A.

International Journal of Microelectronics and Computer Science

2016

Vol. 7, nr 4

147--156

The protection of information that reside in smart devices like IoT nodes is becoming one of the main concern in modern design. The possibility to mount a non-invasive attack with no expensive equipment, such as a Power Analysis Attack (PAA), remarks the needs of countermeasures that aims to thwart attacks exploiting power consumption. In addition to that, designers have to deal with demanding requirements, since those smart devices require stringent area and energy constraints. In this work, a novel analog-level approach to counteract PAA is presented, taking benefits of the current-mode approach. The kernel of this approach is that the information leakage exploited in a PAA is leaked through current absorption of a cryptographic device. Thanks to an on-chip measuring of the current absorbed by the cryptographic logic, it is possible to generate an error signal. Throughout a current-mode feedback mechanism, the data-dependent component of the overall consumption can be compensated, making the energy requirement constant at any cycle and thwarting the possibility to recover sensible information. Two possible implementations of the proposed approach are presented in this work and their effectiveness has been evaluated using a 40nm CMOS design library. The proposed approach is able to increase the Measurements to Disclosure (MTD) of at least three orders of magnitude, comparing to the unprotected implementation. It has to be pointed out that the on-chip current-mode suppressor, based on the proposed approach, is able to provide a very good security performance, while requiring a very small overhead in terms of silicon area (xl.007) and power consumption (xl.07).