Wyniki wyszukiwania - BazTech

1

Surface forces in chemical mechanical planarization and semiconductor wafer cleaning systems

Hupka Lukasz, Nalaskowski Jakub, Miller Jan D., Hupka Jan

Wiadomości Chemiczne

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2021

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[Z] 75, 9-10

1229--1240

EN

Superior uniformity and local planarity of semiconductor wafers in the chemical mechanical planarization (CMP) process as well as efficient post-CMP cleaning is controlled by surface chemistry phenomena. The AFM colloidal probe technique was used to demonstrate surface forces which are of special significance to CMP and post-CMP cleaning. Examples of ways to manipulate those interactions are provided, and the benefits to CMP processes and post-CMP cleaning are discussed.

2

Fifty years of stacking

Rashed M.

Acta Geophysica

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2014

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Vol. 62, no. 3

505--528

EN

Common-Mid-Point (CMP) stacking is a major process to enhance signal-to-noise ratio in seismic data. Since its appearance fifty years ago, CMP stacking has gone through different phases of prosperity and negligence within the geophysical community. During those times, CMP stacking developed from a simple process of averaging into a sophisticated process that involves complicated mathematics and state-of-the-art computation. This article summarizes the basic principles, assumptions, and violations related to the CMP stacking technique, presents a historical overview on the development stages of CMP stacking, and discusses its future potentiality.

3

Location of Processor Allocator and Job Scheduler and Its Impact on CMP Performance

Zydek D., Chma G., Shawky A., Selvaraj H.

International Journal of Electronics and Telecommunications

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2012

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Vol, 58, No. 1

9-14

EN

High Performance Computing (HPC) architectures are being developed continually with an aim of achieving exascale capability by 2020. Processors that are being developed and used as nodes in HPC systems are Chip Multiprocessors (CMPs) with a number of cores. In this paper, we continue our effort towards a better processor allocation process. The Processor Allocator (PA) and Job Scheduler (JS) proposed and implemented in our previous works are explored in the context of its best location on the chip. We propose a system, where all locations on a chip can be analyzed, considering energy used by Network-on-Chip (NoC), PA and JS, and processing elements. We present energy models for the researched CMP components, mathematical model of the system, and experimentation system. Based on experimental results, proper placement of PA and JS on a chip can provide up to 45% NoC energy savings.

4

Energy characteristic of a processor allocator and a network-on-chip

Zydek D., Selvaraj H., Borowik G., Łuba T.

International Journal of Applied Mathematics and Computer Science

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2011

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Vol. 21, no 2

385-399

EN

Energy consumption in a Chip MultiProcessor (CMP) is one of the most important costs. It is related to design aspects such as thermal and power constrains. Besides efficient on-chip processing elements, a well-designed Processor Allocator (PA) and a Network-on-Chip (NoC) are also important factors in the energy budget of novel CMPs. In this paper, the authors propose an energy model for NoCs with 2D-mesh and 2D-torus topologies. All important NoC architectures are described and discussed. Energy estimation is presented for PAs. The estimation is based on synthesis results for PAs targeting FPGA. The PAs are driven by allocation algorithms that are studied as well. The proposed energy model is employed in a simulation environment, where exhaustive experiments are performed. Simulation results show that a PA with an IFF allocation algorithm for mesh systems and a torus-based NoC with express-virtual-channel flow control are very energy efficient. Combination of these two solutions is a clear choice for modern CMPs.

5

Evaluation of MOSFETs with crystalline high-k gate-dielectrics: device simulation and experimental data

Zaunert F., Endres R., Stefanov Y., Schwalke U.

Journal of Telecommunications and Information Technology

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2007

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nr 2

78-85

EN

The evaluation of the world's first MOSFETs with epitaxially-grown rare-earth high-k gate dielectrics is the main issue of this work. Electrical device characterization has been performed on MOSFETs with high-k gate oxides as well as their reference counterparts with silicon dioxide gate dielectric. In addition, by means of technology simulation with TSUPREM4, models of these devices are established. Current-voltage characteristics and parameter extraction on the simulated structures is conducted with the device simulator MEDICI. Measured and simulated device characteristics are presented and the impact of interface state and fixed charge densities is discussed. Device parameters of high-k devices fabricated with standard poly-silicon gate and replacement metal gate process are compared.

6

Plazma indukcyjnie sprzężona - jej rola w emisyjnej spektrometrii atomowej

Müller E., Bolibrzuch B.

Analityka : nauka i praktyka

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2002

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nr 3

18--19

PL

Emisyjna spektrometria atomowa jest jedną z najpowszechniej stosowanych technik analitycznych w analizie elementarnej. Swoje szerokie zastosowanie zarówno w laboratoriach badawczych, jak i przemysłowych zawdzięcza możliwości równoczesnego oznaczania wielu pierwiastków przy zachowaniu dużej precyzji i dokładności w szerokim zakresie.