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Characteristics of an image sensor with early-vision processing fabricated in standard 0.35 žm CMOS technology

Jendernalik W., Jakusz J., Blakiewicz G., Szczepański S., Piotrowski R.

Metrology and Measurement Systems

2012

Vol. 19, nr 2

191-202

The article presents measurement results of prototype integrated circuits for acquisition and processing of images in real time. In order to verify a new concept of circuit solutions of analogue image processors, experimental integrated circuits were fabricated. The integrated circuits, designed in a standard 0.35 žm CMOS technology, contain the image sensor and analogue processors that perform low-level convolution-based image processing algorithms. The prototype with a resolution of 32 x 32 pixels allows the acquisition and processing of images at high speed, up to 2000 frames/s. Operation of the prototypes was verified in practice using the developed software and a measurement system based on a FPGA platform.

CMOS realisation of analogue processor for early vision processing

Jendernalik W., Jakusz J., Blakiewicz G., Piotrowski R., Szczepański S.

Bulletin of the Polish Academy of Sciences. Technical Sciences

2011

Vol. 59, nr 2

141-147

The architecture concept of a high-speed low-power analogue vision chip, which performs low-level real-time image algorithms is presented. The proof-of-concept prototype vision chip containing 32 �~ 32 photosensor array and 32 analogue processors is fabricated using a 0.35 mikrom CMOS technology. The prototype can be configured to register and process images with very high speed, reaching 2000 frames per second, or achieve very low power consumption, several mikroW. Finally, the experimental results are presented and discussed.