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1

On analog comparators for CMOS digital pixel applications. A comparative study

Jendernalik W.

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2016

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Vol. 64, nr 2

271--278

EN

Voltage comparator is the only - apart from the light-to-voltage converter - analog component in the digital CMOS pixel. In this work, the influence of the analog comparator nonidealities on the performance of the digital pixel has been investigated. In particular, two versions of the digital pixel have been designed in 0.35 μm CMOS technology, each using a different type of analog comparator. The properties of both versions have been compared. The first pixel utilizes a differential comparator with the increased size and improved electrical performance. The second structure is based on a very simple non-differential comparator with a reduced size and degraded performance. Theoretical analysis of the comparator nonideality effect on the quality of the image obtained from the digital pixel matrix as well as simulation results are provided.

2

Prosty komparator analogowydla cyfrowego przetwornika obrazu CMOS

Jendernalik W.

Przegląd Elektrotechniczny

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2015

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R. 91, nr 9

85-88

PL

Komparator napięciowy, oprócz przetwornika światło-napięcie, jest jedynym elementem analogowym w cyfrowym pikselu CMOS. W pracy badano wpływ nieidealności komparatora analogowego na parametry cyfrowego piksela. W tym celu zaprojektowano w technologii CMOS 0,35 μm dwie wersje cyfrowego piksela, różniące się typem zastosowanego komparatora analogowego. W pierwszej wersji piksela zastosowano różnicowy komparator o zwiększonej powierzchni topografii i polepszonych własnościach elektrycznych. W drugiej wersji zastosowano bardzo prosty nieróżnicowy komparator o zmniejszonej powierzchni i gorszych własnościach elektrycznych. Przedstawiono analizę teoretyczną wpływu nieidealności komparatora na jakość obrazu (szum typu FPN) uzyskiwanego z matrycy cyfrowych pikseli i przedstawiono wyniki symulacji komputerowych.

EN

A voltage comparator, in addition to the light-to-voltage converter, is the only analogue part of the CMOS digital pixel. In this work, the influence of an analogue comparator nonidealities on the digital pixel’s parameters was investigated. For this purpose, it was designed in 0.35 μm CMOS technology two versions of the digital pixel, which differ in the type of an analogue comparator used. In the first version of the pixel is used a differential comparator with a larger layout area and an improved electrical parameters. In the second version, is used a very simple single-ended comparator with a reduced layout area and a worse electrical properties. The analytical analysis of the influence of a comparator nonidealities on an image quality (FPN noise) from the array of the digital pixels is presented. The simulation results are also presented.

3

Performance Evaluation of Fabless CMOS Image Sensor Design Houses by Using an Multiple Objective Programming Based Data Envelopment Analysis

Chen H., Huang C.-Y.

Przegląd Elektrotechniczny

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2012

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R. 88, nr 7b

289--293

EN

Complementary Metal Oxide Semiconductor (CMOS) image sensors have widely been used due to the advantages in terms of low power consumption, on-chip signal processing capability, and a comparatively low cost. The market research institutes predicted that the demand for CMOS image sensors will dramatically increase over the next few years. Although the demand continues to increase, the market is becoming daily competitive. Thus, operating efficiently will be very critical for CMOS image sensor vendors to sustain competitiveness. The fabless CMOS image sensor design is one of the fast emerging and most important sectors of the CMOS image sensor industry. Understanding the efficiency of fabless CMOS image sensor design houses is critical for managers of the fabless CMOS image sensor design houses, semiconductor foundries as well as investors. Albeit critical, very few scholars tried to evaluate the performance of the fabless CMOS image sensor vendors. Thus, this paper aims to evaluate the productivity and efficiency of CMOS image sensor firms. A novel Multiple Objectives Programming based Data Envelopment Analysis (DEA) model will be introduced for benchmarking the firms.

PL

Opisano projektowanie czujnika obrazu CMOS. Wprowadzono nowy algorytm DEA (data envelopment analysis) do oprogramowania MOP (multiple objective programming).

4

Cost-effective image acquisition system for precise PC-based measurement

Pribula O., Sedivy J., Fischer J.

Przegląd Elektrotechniczny

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2011

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R. 87, nr 7

259-263

EN

Image sensors based on the CMOS technology became commonly used sources of image information in PC-based vision systems. Image information is converted directly on the chip to a stream of synchronous digital data which can be transferred to a PC using the cost-effective interface introduced in this contribution. The CMOS image sensor together with the developed interface can be considered as a simple image acquisition system - USB camera matching all features of distributed image acquisition and processing model described in this article. Concept of the USB camera is enhanced by additional data merged with each image frame transferred to the PC. This feature makes the developed device suitable for tasks where the precise timing of image acquisition together with an external synchronization is required. Based on the VHDL model of the used CMOS image sensor and the designed PC interface with the USB driver, the critical timing and maximal USB data throughput limitations are analyzed and discussed.

PL

Informacja o obrazie z czujnika obrazu typu CMOS jest bezpośrednio przetwarzana w strumień transferowany do komputera. Kamera USB może być traktowana jako system pobierania i przetwarzania informacji. W artkule analizowany jest taki system, a szczególnie timing i szybkość przepływu danych.

5

Reduction of random telegraph signal (RTS) noise in CMOS image sensors using histogram analysis

bin Mustafa M. A., Itoh S., Kawahito S.

Journal of Automation Mobile Robotics and Intelligent Systems

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2009

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Vol. 3, No. 4

202-203

EN

The paper presents column parallel signal processing techniques for reducing Random Telegraph Signal (RTS) noise of in-pixel source follower by using histogram analysis for the development of a very low-noise CMOS image sensor. In this method, a histogram with multiple samples for reset level is used to estimate the amplitude of the RTS noise. With the median of the histogram and the estimated amplitude, the RTS noise components are removed and the average is calculated with the histogram due to thermal noise only, to further reduce the noise level. Result of the application of the histogram-based noise suppres-sion to an implemented CMOS image sensor prototype for a large sampling numbers is demonstrated.

6

Diffractive optical filters

Kozik S., Manak I., Smirnov A.

Przegląd Elektrotechniczny

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2008

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R. 84, nr 3

64-66

EN

In this paper, we demonstrate the feasibility of three color filter design for the visible range. We analyze limitations and provide optimization of diffractive filters based on one-dimensional patterned metal layers. We present result of numerical simulation for a novel design, which exhibits two-side bounded transmittance spectra with similar shape for different polarizations of incident radiation. The operating wavelength of the structure is smaller than period of patterns used, thus reducing the critical dimension requirement for fabrication technology.

PL

Przedstawiono projektowanie trzykolorowego filtru. Przeanalizowano ograniczenia I przeprowadzono optymalizację filtru dyfrakcyjnego wykorzystującego jednowymiarową warstwę metalu. Przedstawiono rezultaty symulacji numerycznej nowego projektu, który wykazuje dwustronne brzegowe widmo transmitancji o podobnym kształcie dla różnych polaryzacji. Zakres fal proponowanej struktury jest mniejszy niż użyty wzór, a więc wymaga technologii redukującej rozmiary krytyczne.

7

Noise minimization via deep submicron system-on-chip integration in megapixel CMOS imaging sensors

Kozlowski L. J.

Opto-Electronics Review

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2006

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Vol. 14, No. 1

11-18

EN

Infrared sensor designers have long maximized S/N ratio by employing pixel-based amplification in conjunction with supplemental noise suppression. Instead, we suppress photodiode noise using novel SoC implementation with simple three transistor pixel; supporting SoC components include a feedback amplifier having elements distributed amongst the pixel and column buffer, a tapered reset clock waveform, and reset timing generator. The tapered reset method does not swell pixel area, compel processing of the correlated reset and signal values, or require additional memory. Integrated in a 2.1 M pixel imager developed for generating high definition television, random noise is ~8e- at video rates to 225 MHz. Random noise of ~30e would otherwise be predicted for the 5 µm by 5 µm pixels having 5.5 fF detector capacitance with negligible image lag. Minimum sensor S/N ratio is 52 dB with 1920 by 1080 progressive readout at 60 Hz, 72 Hz and 90 Hz. Fixed pattern noise is <2 DN via on-chip signal processing.