PL
 |
EN
Preferencje help
Polish version English version Język
Widoczny [Schowaj] Abstrakt
Liczba wyników

Znaleziono wyników: 5

Liczba wyników na stronie
first rewind previous Strona / 1 next fast forward last
Wyniki wyszukiwania
Wyszukiwano:
w słowach kluczowych:  CMOS analog circuits
help Sortuj według:

help Ogranicz wyniki do:
first rewind previous Strona / 1 next fast forward last
1
Content available Fully Analytical Characterization of the Series Inductance of Tapered Integrated Inductors
Passos F., Fino M. H., Moreno E. R.
International Journal of Electronics and Telecommunications
|
2014
|
Vol. 60, No. 1
73-77
EN
In this paper a general method for the determination of the series inductance of polygonal tapered inductor s is presented. The value obtained can be integrated into any integrated inductor lumped element model, thus granting the overall characterization of the device and the evaluation of performance parameters such as the quality factor or the resonance frequency. In this work, the inductor is divided into several segments and the corresponding self and mutual inductances are calculated. In the end, results obtained for several working examples are compared against electromagnetic (EM) simulations are performed in order to check the validity of the model for square, hexagonal, octagonal and tapered inductors. The proposed method depends exclusively on the geometric characteristics of the inductor as well as the technological parameters. This allows its straight forward application to any inductor shape or technology.
2
Content available Cascode amplifiers with low-gain variability and gain enhancement using a body-biasing technique
Pereira N, Oliveira L. B., Goes J., Oliveira J. P.
International Journal of Microelectronics and Computer Science
|
2013
|
Vol. 4, nr 3
98--102
EN
This paper presents a simple circuit technique to reduce gain variability with PVT variations in cascode amplifiers using a body-biasing scheme, while enhancing the overall gain of the amplifier. Simulation results of a standard telescopic-cascode amplifier, in two different nanoscale CMOS technologies (130 nm and 65 nm) show that the proposed compensated circuit amplifier exhibits a (DC) gain variability smaller (below ± 0.5 dB) than the original (uncompensated) circuit, while reaching a gain enhancement of about 3 dB. The required auxiliary biasing circuit dissipates around 5% of the main amplifier circuit.
3
Content available remote Regulowany Multiplikator Pojemności w Technologii CMOS
Kulej T.
Przegląd Elektrotechniczny
|
2012
|
R. 88, nr 1b
227-230
PL
W pracy przedstawiono nowe rozwiązanie regulowanego multiplikatora pojemności w technologii CMOS 50nm. Prezentowany układ charakteryzuje się bardzo małą wartością napięcia zasilania (0,5V) i mocy rozpraszanej (22nW-213nW). Układ umożliwia multiplikację pojemności w zakresie 5-100 razy, przy zachowaniu odpowiednio dobrych parametrów układowych takich jak dynamika, prąd niezrównoważenia czy zakres częstotliwości pracy.
EN
A novel solution for capacitance multiplier in 50 nm CMOS is presented in the paper. The circuit is characterized by low supply voltage (0.5V), very low dissipation power (22nW-213nW). The capacitance multiplying factor can be varied in a wide range (5-100), while keeping good electrical parameters such as offset current, dynamic and frequency range.
4
Content available remote Niskonapięciowy filtr bikwadratowy CMOS, pracujący w trybie prądowym na zakres małych częstotliwości
Kulej T.
Przegląd Elektrotechniczny
|
2011
|
R. 87, nr 8
219-222
PL
W pracy przedstawiono rozwiązanie mikromocowego filtru bikwadratowego CMOS, pracującego w trybie prądowym. Struktura filtru oparta jest o nowy układ zwierciadła prądowego , wykorzystujący tranzystory sterowane z elektrody podłożowej. Dzięki temu uzyskano linearyzację charakterystyk filtru i bardzo małą wartość napięcia zasilania, równą 0,5V.
EN
A novel solution for a low-power current-mode biquad filter in CMOS technology is described in the paper. The circuit structure is based on a new current mirror realized with bulk-driven transistors. Thanks to this, linear circuit characteristics are obtained for supply voltages as low as 0,5V.
5
Content available remote Transresistance CMOS neuron for adaptive neural networks implemented in hardware
Wojtyna R., Talaśka T.
Bulletin of the Polish Academy of Sciences. Technical Sciences
|
2006
|
Vol. 54, nr 4
443-448
EN
A simple analog circuit is presented which can play a neuron role in static-model-based neural networks implemented in the form of au integrated circuit. Operating in a transresistance mode it is suited to cooperate with transconductance synapses. As a result, its input signal is a current which is a sum of currents coming from the synapses. Summation of the currents is realized in a made at the neuron input. The circuit bas two outputs and provides a step function signal at one output and a linear function one at the other. Activation threshold of the step output can be conveniently controlled by means of a voltage. Having two outputs, the neuron is attractive to be used in networks taking advantage of fuzzy logic. It is built of only five MOS transistors, can operate with very law supply voltages, consumes a very law power when processing the input signals, and no power in the absence of input signals. Simulation as well as experimental results are shown to be in a good agreement with theoretical predictions. The presented results concern a 0.35 [mi]m CMOS process and a prototype fabricated in the framework of Europractice.
first rewind previous Strona / 1 next fast forward last
JavaScript jest wyłączony w Twojej przeglądarce internetowej. Włącz go, a następnie odśwież stronę, aby móc w pełni z niej korzystać.