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Performance Targeted Synthesis of ASM Controllers on FPGA

Salauyou V., Bulatowa I.

Measurement Automation Monitoring

2018

Vol. 64, No. 2

31--33

Performance-driven synthesis of controller circuits is very important and challenging task in digital systems design. The clock frequency of a synchronous sequential logic circuit is dependent in a large part on the maximum propagation delay through its combinational block. The paper presents a new method for FPGA-based design of high-speed Algorithmic State Machine (ASM) controllers. The proposed approach is based on the introduction of additional states of the state machine in order to simplify transition and output logical functions to implement them in the single-level structures. The proposed technique is applied at the stage of converting the ASM chart to the finite state machine description and allows obtaining such an HDL specification that provides an increase in the designed system speed. Experimental results show that our approach achieves an average performance gain of 22.24% to 29.72% (for various FPGA devices) compared with the conventional synthesis method.

Synteza hierarchicznych struktur automatów mikroprogramowalnych

Salauyou V., Bułatova I.

Pomiary Automatyka Kontrola

2012

R. 58, nr 7

599-601

Przedstawiono metodę syntezy hierarchicznych struktur automatów mikroprogramowalnych, algorytmy sterowania których opisywane są za pomocą sieci działań. Metoda syntezy umożliwia realizację złożonych układów sterowania w postaci sieci hierarchicznie podporządkowanych automatów. Opracowany został algorytm dekompozycji sieci działań na fragmenty realizowane jako komponenty struktury hierarchicznej. Przeprowadzono badania wpływu parametrów sieci działań na możliwość oraz koszt realizacji struktury hierarchicznej.

In this paper a method for synthesis of hierarchical structures of microprogram automata specified by the Algoritmic State Machine (ASM) charts [4] is presented. The proposed method enables the synthesis of complex control systems as a network of hierarchically subordinated automata (Fig. 1), each of which can be implemented on a separate PLD device with limited parameters. Two-level hierarchical structure can also be used to implement control algorithms with repeated fragments [6]. In this approach each repeated section is implemented in the structure only once, and is called many times during the algorithm execution. Additionally, a modified hierarchical structure that allows parallel execution of algorithm fragments is proposed (Fig. 4). The algorithm of decomposition of the ASM chart into fragments which are implemented as components of a hierarchical structure was developed. The synthesis algorithm considers limitations on the fragments size and minimizes the number of links between the different automata. The conditions the expediency of ASM decomposition into fragments to be implemented in a separate automata of the hierarchical structure are taken into consideration, too. A prerequisite for implementation of the method is decomposition of the ASM to fragments having only one input and one output, which is not always possible to fulfill. The experimental results show how the possibility of realization and the cost of implementation of the microprogram automata hierarchical structures depend on the parameters of the ASM charts.