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1 Prace Przemysłowego Instytutu Elektroniki

1 1998

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A "bit-flipping" approach to multistage two-path decimation filter design

Krukowski A., Kale I., Cain G., Hejn K.

Prace Przemysłowego Instytutu Elektroniki

1998

nr 132

42-51

This paper presents a design technique for high fidelity multistage decimation filters based on the polyphase decimator structures presented by Constantinides et al, catering for powers of two sample-rate decreases. The technique is well suited for Analog-to-Digital Convener (ADC) applications in excess of 16-bit resolution. The resulting filter coefficients are constrained to the required bit length using a "bit-flipping algorithm" This technique illustrated in the context of an example of a cascaded decimation filter, designed for a 20-bit resolution ADC. and compared to other approximation methods. The resulting coefficient values and frequency responses of the cascaded filters are reported