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1
Content available Spice simulation of substrate potential shift in HVCMOS technologies
Stefanucci C., Buccella P., Kayal M., Sallese J.-M.
International Journal of Microelectronics and Computer Science
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2015
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Vol. 6, nr 4
142--147
EN
High voltage CMOS active devices inherently include a parasitic vertical PNP bipolar transistor. When activated it injects holes into the substrate causing a dangerous potential shift. In this work a spice-modeling approach based on transistor layout is presented to simulate substrate de-biasing in Smart Power ICs. The proposed model relies on a parasitic substrate network without the need of a parasitic BJT in HVCMOS compact models. The results are compared with TCAD simulations at different temperatures showing good agreement. Potential shift of the substrate is analysed for different geometrical configurations to estimate the effect of P+ grounding schemes and backside contact.
2
Content available SPICE simulation of passive N-type guard rings in smart power ICs
Buccella P., Stefanucci C., Sallese J.-M., Kayal M.
International Journal of Microelectronics and Computer Science
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2015
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Vol. 6, nr 2
64--68
EN
When designing in Smart Power technologies, TCAD simulations are mandatory to design effective passive protections against parasitic couplings due to minority carriers. The objective of this paper is to propose a SPICE-based approach to characterize electrical key parameters of a passive protection directly within standard IC design flow avoiding time consuming TCAD simulations. Our approach consists in integrating a new substrate model in SPICE to enable designers to derive themselves process specific design rules and reduce substrate couplings. This methodology enables designers to access valuable results in the early stage of IC design, where before such results could be obtained only in the final verification step.
3
Content available Downscaling and short channel effects in twin gate junctionless vertical slit FETs
Barbut L, Jazaeri F, Bouvet D, Sallese J.-M.
International Journal of Microelectronics and Computer Science
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2013
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Vol. 4, nr 3
103--109
EN
In this work, we present the performance constraints in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier lowering is investigated with respect to key technological parameters, namely, the doping level in the channel, the minimum slit width, and the effective radius of the slit. This work could serve as a guideline for technology optimization, design and scaling of JL VeSFETs.
4
Content available Hall effect sensors performance investigation using three-dimensional simulations
Paun M.-A., Sallese J.-M., Kayal M.
International Journal of Microelectronics and Computer Science
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2011
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Vol. 2, nr 4
140-145
EN
Several Hall effect sensors were modeled and evaluated regarding the Hall voltage and sensitivity using 3D physical simulations. For accurate results the numerical offset and its temperature drift were analyzed. The versatility of the simulation allows various Hall sensor implementations. The simulation procedure could guide the designer in choosing the Hall cell optimum fabrication process, shape and dimensions in terms of the performances envisaged to be achieved.
5
Content available Measurement and performance evaluation of a silicon on insulator pixel matrix
Ntavelis D., Harik L., Sallese J.-M., Kayal M., Hatzopoulos A.
International Journal of Microelectronics and Computer Science
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2010
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Vol. 1, nr 3
299-304
EN
A new technique for driving silicon-on-insulator pixel matrixes has been proposed in |1|, which was based on transient charge pumping for evacuating the extra photo-generated charges from the body of the transistor. An 8x8 pixel matrix was designed and fabricated using the above technique. In this paper, the measurement set-up is described and the performance evaluation procedure is given, together with results of its implementation on the fabricated pixel matrix. The results show the applicability of the charge pumping technique and the effective operation of the image sensor.
6
Content available Advanced compact modeling of the deep submicron technologies
Grabiński W., Bucher M., Sallese J.-M., Krummenacher F.
Journal of Telecommunications and Information Technology
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2000
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nr 3-4
31-42
EN
The technology of CMOS large-scale integrated circuits (LSI's) achieved remarkable advances over last 25 year and the progress is expected to continue well into the next century. The progress has been driven by the downsizing of the active devices such as MOSFETs. Approaching these dimensions, MOSFET characteristics cannot be accurately predicted using classical modeling methods currently used in the most common MOSFET models such as BSIM, MM9 etc, without introducing large number of empirical parameters. Various physical effects that needed to be considered while modeling UDSM devices: quantization of the inversion layer, mobility degradation, carrier velocity saturation and overshoot, polydepletion effects, bias dependent source/drain resistances and capacitances, vertical and lateral doping profiles, etc. In this paper, we will discuss the progress in the CMOS technology and the anticipated difficulties of the sub-0.25 žm LSI downsizing. Subsequently, basic MOSFET modeling methodologies that are more appropriate for UDSM MOSFETs will be presented as well. The advances in compact MOSFET devices will be illustrated using application examples of the EPFL EKV model
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