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2 International Journal of Microelectronics and Computer Science

2 2017

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A novel high-swing high-speed with 187 µW power consumption Common-Mode Feedback Block (CMFB) based on rail-to-rail technique

Mahdavi S., Noruzpur F., Ghadimi E., Khanshan T. M.

International Journal of Microelectronics and Computer Science

2017

Vol. 8, nr 2

50--56

This paper presents a new high-swing, high-speed and low power continuous-time Common-Mode Feedback Block (CMFB) based on rail-to-rail technique. The main purposes of the proposed idea are to achieve high-speed, low settling time error, large output swing, and low power as well. Moreover, applying the worst case simulation (initial condition 0 and 1.8 volts) on the proposed CMFB circuit, the output voltage can be settled in the desired level just after 1.18ns noticeably. The settling time error and the power consumption of the suggested common-mode feedback circuit are just 103|iV and 187µW with the power supply of 1.8 volts respectively. Meanwhile, DC gain and phase margin of the amplifier are 74dB and 67 degree correspondingly, and 0.5pF capacitor load is applied to the output nodes of the amplifier. It is noteworthy that, the proposed idea is a good candidate for low voltage applications too. Because it just needs 2 overdrive voltage (AV) to start its performance. Applying the proposed idea on the folded cascode amplifier it achieves SNDR of 68.68dB with the Effective Number of Bits (ENOB) 11.15 bits respectively. The proposed CMFB occupies an active area of 155.58µm2 (10.56µm*14.73µm). Finally, the proposed structure is simulated in whole process corner condition and different temperatures from -70°C to +70°C. Simulation results are performed using the HSPICE BSIM3 model of a 0.18µm CMOS technology.

1.25GS/S 12bit and 2.27mW digital to analog converter (DAC) with 70.22 SNDR based on new hybrid R-C procedure in 180nm CMOS

Mahdavi S., Poreh M., Alizadeh L., Moradkhani B., Ebrahimi R.

International Journal of Microelectronics and Computer Science

2017

Vol. 8, nr 4

127--132

This paper presents a novel fully differential high-speed and high-resolution Digital to Analog Converter (DAC) based on new reliable hybrid R-C technique. In the proposed idea the four LSB bits and eight MSB bits are implemented as a resistor string and new merged capacitor technique respectively. Applying the suggested method the SNDR and Effective Number of Bits (ENOB) of the proposed DAC achieve 70.22dB and 11.41 bit at the 1.25GS/s sampling rate correspondingly. In the proposed method the total capacitors of the 8 MSB bits are reduced up to 78% compared to the conventional one noticeably. As a result, the power consumption and speed of the suggested DAC are decreased and increased respectively. Moreover, the total power consumption of the proposed DAC is 2.27mW with the power supply of 1.8 volts as well. Meanwhile, for the correctness of the proposed 12bit DAC, 200 iterations in transient Monte-Carlo analysis (parasitic capacitance included ([symbol] mismatch = 1.2%)), and the SNDR simulation results versus different input frequency at fS=1.25GS/s sampling rate are applied too. The maximum Integral Nonlinearity (INL) and the maximum Differential Nonlinearity (DNL) are -0.47/+0.35LSB and -0.42/+0.29 LSB respectively. The proposed DAC structure is simulated in all process corners and performed using the HSPICE BSIM3 model of a 0.18μm CMOS technology.