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Compact Transverse Electric Silicon-on-Insulator Mode Converter for Mode-Division Multiplexer

Sharaf Mohamed H., El-Mashade Mohamed B., Emran Ahmed A.

International Journal of Electronics and Telecommunications

2022

Vol. 68, No. 2

275--280

On-chip optical-interconnect technology emerges as an attractive approach due to its ultra-large bandwidth and ultra-low power consumption. Silicon-on-insulator (SOI) wire waveguides, on the other hand, have been identified to potentially replace copper wires for intra-chip communication. To take advantage of the wide bandwidth of SOI waveguides, wavelengthdivision multiplexing (WDM) has been implemented. However, WDM have inherent drawbacks. Mode-division multiplexing (MDM) is a viable alternative to WDM in MIMO photonic circuits on SOI as it requires only one carrier wavelength to operate. In this vein, mode converters are key components in on-chip MDM systems. The goal of this paper is to introduce a transverse electric mode converter. The suggested device can convert fundamental transverse electric modes to first-order transverse electric ones and vice versa. It is based on small material perturbation which introduces gradual coupling between different modes. This device is very simple and highly compact; the size of which is 3 μm². Mathematical expressions for both the insertion loss and crosstalk are derived and optimized for best performance. In addition, three-dimensional finite-difference time-domain (3D-FDTD) simulations are performed in order to verify the mathematical model of the device. Our numerical results reveal that the proposed device has an insertion loss of 1.2 dB and a crosstalk of 10.1 dB. The device’s insertion loss can be decreased to 0.95 dB by adding tapers to its material perturbation.

A New Design Methodology For Enhancing The Transient Loading Of Low Drop-out Regulators (LDRs)

Abdel-Monem Ahmed, El-Mashade Mohamed B., Dabbous T. E.

International Journal of Electronics and Telecommunications

2019

Vol. 65, No. 2

319--327

A new simple design methodology which makes LDR output nearly insensitive to jumps of the load current for long times is proposed. This methodology is tested for more than 10⁴ seconds. Our procedure leans on cross coupling of the time second derivative of the LDR power transistor gate and drain voltages along with their currents. This technique keeps low values of these currents in order of nano or hundreds of micro amperes for undershot or overshot cases, respectively. The introduced methodology has been applied to a standard CMOS of 0.18μm technology for NMOS transistors and validated using MATLAB R2014a.