Rapid progress in multimedia computing and communications technologies imposes a very high level of performance requirements for the underlying VSLI technology. The concept of personal interactive mobile multimedia communicator (M³C) [11] requires very high performance in terms of processing speed and the associated power-area product. Portability of the system imposes further complexity in terms of the need for low voltage operation. For ultra-fast systems a considerable part of power is dissipated within a clock generation and distribution system. At the same time, at Gigahertz frequencies the clock skew becomes the factor limiting the speed of the system. This paper presents the design methodology for highly pipelined, self-timed building blocks suitable for mulimedia applications using Gallium Arsenide MESFET [18,19] as the base technology implementation of latched logic design style (PDLL, LCFL) [6, 9, 12, 13]. The use of latched logic together with the absence of the global clock provides for low power dissipation while maintaining very high speed of the system.
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