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EN
This paper presents a new method for analog circuit design optimization. Our approach turns to good account the advantages offered by computational intelligence techniques. Design objectives can be expressed in a flexible manner using fuzzy sets. This way appears the possibility to consider different degrees for requirement achievements and acceptability degree for a particular solution. Neuro-fuzzy systems (universal approximators) are used to model the complex multi-variable and nonlinear circuit performances. These models satisfy two main requirements: high accuracy and low computation complexity. An efficient and robust genetic algorithm does avoiding local minima the exploration of the large, multidimensional solution space in quest for the optimal solution.
3
Content available An analog linear SVM image classifier
EN
A linear Support Vector machine classifier is proposed in this paper. In such SVM architectures based on multiplying laws the main building blocks are multipliers. We propose in this paper multiplying and weighting cells, developed by using a model consisting of a compound of two inverse non-linear functions. This procedure is suitable for VLSI implementation because it permits the use of simple nonlinearized standard log-domain or DA cells that compensate each other nonlinearities to obtain an extended domain of operation. Current-mode ELIN (externally linear internally nonlinear) design is used for its low voltage, low power and high speed characteristics. The resulted parallel-serial classifier was simulated taking into account real parameters of transistors in BICMOS technology.
EN
This paper presents a reconfigurable and programmable analogue low pass filter for low voltage wireless applications. The proposed filter may be used for channel or band selection in multi-mode receiver front ends employing direct frequency conversion. The circuit has been synthesized using state variables and leapfrog OTA-C techniques, features programmable order, digitally variable frequency parameters and wide linear range. The fundamental OTA cell has been implemented with fully balanced second-generation current conveyors, suitable for operating with low supply voltages. Transistor level simulations based on a 180 nm digital CMOS technology have demonstrated the functionality of the design.
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