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1

FPGA implementation of procedures for video quality assessment

Wielgosz M., Karwatowski M., Pietron M., Wiatr K.

Computer Science

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2018

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Vol. 19 (3)

279--305

EN

The video resolutions used in a variety of media are constantly rising. While manufacturers struggle to perfect their screens, it is also important to ensure the high quality of the displayed image. Overall quality can be measured using a Mean Opinion Score (MOS). Video quality can be affected by miscellaneous artifacts appearing at every stage of video creation and transmission. In this paper, we present a solution to calculate four distinct video quality metrics that can be applied to a real-time video quality assessment system. Our assessment module is capable of processing 8K resolution in real time set at a level of 30 frames per second. The throughput of 2.19 GB/s surpasses the performance of pure software solutions. The module was created using a high-level language to concentrate on architectural optimization.

2

Assessment of various GPU acceleration strategies in text categorization processing flow

Korduła Ł., Wielgosz M., Karwatowski M., Pietroń M., Żurek D., Wiatr K.

Measurement Automation Monitoring

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2017

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Vol. 63, No. 6

203--205

EN

Automatic text categorization presents many difficulties. Modern algorithms are getting better in extracting meaningful information from human language. However, they often significantly increase complexity of computations. This increased demand for computational capabilities can be facilitated by the usage of hardware accelerators like general purpose graphic cards. In this paper we present a full processing flow for document categorization system. Gram-Schmidt process signatures calculation up to 12 fold decrease in computing time of system components.

3

Real time 8K video quality assessment using FPGA

Wielgosz M., Pietroń M., Karwatowski M., Wiatr K.

Measurement Automation Monitoring

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2016

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Vol. 62, No. 6

187--189

EN

This paper presents a hardware architecture of the video quality assessment module. Two different metrics were implemented on FPGA using modern High Level Language for digital system design – Impulse C. FPGA resources consumption of the presented module is low, which enables module-level parallelization. Tests conducted for four modules working concurrently show that 1.96 GB/s throughput can be achieved. The module is capable of processing 8K video stream in a real-time manner i.e. 30 frames/second. Such high performance of the presented solution was achieved due to the series of architectural optimization introduced to the module, such as reduction of data precision and reuse of various module components.

4

A custom co-processor for the discovery of low autocorrelation binary sequences

Russek P., Karwatowski M., Jamro E., Wiatr K.

Measurement Automation Monitoring

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2016

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Vol. 62, No. 5

154--156

EN

We present a custom processor that was designed to enhance algorithms of finding Low Autocorrelation Binary Sequences (LABS). Finding LABS is very computationally exhaustive, but no custom computing solutions have been reported in the literature so far. A computational kernel which allowed creating an effective single-purpose processor was determined and an appropriate architecture was proposed. The selected elements of the architecture were coded in High-Level Synthesis (HLS) language to speed up the design process. Afterwards, the processor was verified and tested in Xilinx’s Virtex7 FPGA. At the beginning of the paper, we briefly present the finding LABS problem and its importance. Later, we deliver the algorithm, its custom processor structure, and implementation results in terms of the processor performance, size and power.

5

The Java profiler based on byte code analysis and instrumentation for many-core hardware accelerators

Pietroń M., Karwatowski M., Wiatr K.

Measurement Automation Monitoring

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2015

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Vol. 61, No. 7

385--387

EN

One of the most challenging issues in the case of many and multi-core architectures is how to exploit their potential computing power in legacy systems without a deep knowledge of their architecture. The analysis of static dependence and dynamic data dependences of a program run, can help to identify independent paths that could have been computed by individual parallel threads. The statistics of reusing the data and its size is also crucial in adapting the application in GPU many-core hardware architecture because of specific memory hierarchies. The proposed profiling system accomplishes static data analysis and computes dynamic dependencies for Java programs as well as recommends parts of source code with the highest potential for parallelization in GPU. Such an analysis can also provide starting point for automatic parallelization.

6

A study of parallel techniques for dimensionality reduction and its impact on the quality of text processing algorithms

Pietroń M., Wielgosz M., Karwatowski M., Wiatr K.

Measurement Automation Monitoring

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2015

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Vol. 61, No. 7

352--353

EN

The presented algorithms employ the Vector Space Model (VSM) and its enhancements such as TFIDF (Term Frequency Inverse Document Frequency) with Singular Value Decomposition (SVD). TFIDF were applied to emphasize the important features of documents and SVD was used to reduce the analysis space. Consequently, a series of experiments were conducted. They revealed important properties of the algorithms and their accuracy. The accuracy of the algorithms was estimated in terms of their ability to match the human classification of the subject. For unsupervised algorithms the entropy was used as a quality evaluation measure. The combination of VSM, TFIDF, and SVD came out to be the best performing unsupervised algorithm with entropy of 0.16.