The stude presented in this paper is focused on library development for digital circuit synthesis. An experimental study was made in order to evoluate the impact of the size of the library on the performance of the synthesis process. For these experiments, a collections of 8 libraries based on the same technology and the same standard cells was prepared, with sizes ranging from 218 cells downto 10 cells. A set 5 circuits were used as benchmark material. The results of these benchmarks material. The results of these benchmarks show that the concept of "Reduced ASIC Cell Library" is valid: the loss of performance induced by replacing a 218-cell library by a 17-cell library is not always detectable, and when it is, its typicalvalue is less than 10%, compensated by the of the benefit of faster library development and potential library optimization.
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