Wyniki wyszukiwania - BazTech

1

A Scheduling Strategy for Synchronous Elastic Designs

Carmona J., Cortadella J., Julvez J., Kishinevsky M.

Fundamenta Informaticae

|

2011

|

Vol. 108, nr 1/2

1-21

EN

With the scaling of process technologies, communication delays represent a bottleneck for the performance of circuits. One of the main issues that has to be handled is the variability of such delays. Latency-insensitive circuits offer a form of elasticity that tolerates variations in those delays. This flexibility usually requires the addition of a control layer that synchronizes the flow of information. This paper proposes a method for eliminating the complexity of the control layer, replacing it by a set of iterative schedulers that decide when to activate computations. Unlike previous approaches, this can be achieved with low complexity algorithms and without extra circuitry.

2

Verification of Concurrent Systems with Parametric Delays Using Octahedra

Clarisó R., Cortadella J.

Fundamenta Informaticae

|

2007

|

Vol. 78, nr 1

1-33

EN

A technique for the verification of concurrent parametric timed systems is presented. In the systems under study, each action has a bounded delay where the bounds are either constants or parameters. Given a safety property, the analysis computes automatically a set of constraints on the parameters that is sufficient to guarantee the property. The main contribution is an innovative representation of the parametric timed state space based on bit-vectors. Experimental results from the domain of timed circuits show that this representation improves the efficiency of the verification significantly with a small impact on the accuracy of the derived constraints.

3

Quasi-static Scheduling for Concurrent Architectures

Cortadella J., Kondratyev A., Lavagno L., Taubin A., Watanabe Y.

Fundamenta Informaticae

|

2004

|

Vol. 62, nr 2

171--196

EN

This paper presents a synthesis approach for reactive systems that aims at minimizing the overhead introduced by the operating system and the interaction among the concurrent tasks, while considering multiple concurrent execution resources. A formal model based on the notion of scheduling of Petri nets is used to perform the synthesis. We show how the notion of projections of a schedule for the complete system onto the components implemented on separate resources is essential to define the correctness of the partitioned schedule.

4

A structural encoding technique for the synthesis of asynchronous circuits

Carmona J., Cortadella J., Pastor E.

Fundamenta Informaticae

|

2002

|

Vol. 50, nr 2

135-154

EN

This paper presents a method for the automatic synthesis of asynchronous circuits from Petri net specifications. The method is based on a structural encoding of the system in such a way that a circuit implementation is always guaranteed. Moreover, a set of transformations is presented for the subclass of Free-Choice Petri nets that enables the exploration of different solutions. The set of transformations is derived from previous work on Petri net synthesis. Both the encoding technique and the set of transformations preserve the property of free-choiceness, thus enabling the use of structural methods for the synthesis of asynchronous circuits. Preliminary experimental results indicate that the quality of the circuits is comparable to that obtained by methods that require an exhaustive enumeration of the state space. This novel synthesis method opens the door to the synthesis of large control specifications generated from hardware description languages.