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EN
In this paper a new approach to the design of the high-speed binary-to-residue converter is proposed that allows the attaining of high pipelining rates by eliminating memories used in modulo m generators. The converter algorithm uses segmentation of the input binary word into 2-bit segments. The use and effects of the input word segmentation for the synthesis of converters for five-bit moduli are presented. For the number represented by each segment, the modulo m reduction using a segment modulo m generator is performed. The use of 2-bit segments substantially reduces the hardware amount of the layer of input modulo m generators. The generated residues are added using the multi-operand modulo m adder based on the carry-save adder (CSA) tree, reduction of the number represented by the output CSA tree vectors to the 2m range and fast two-operand modulo m additions. Hardware amount and time delay analyses are also included.
EN
The paper presents results of the high level synthesis of an 1024-point radix-2 FFT processors in Xilinx Vivado FPGA environment. The use of various directives controlling the synthesis process is examined. The results indicate that using the proper set of directives the latency of the processor can be reduced by 95% from about 35k for the default parameters to 1.5k cycles after optimizations.
EN
The paper presents a realization of the scaled residue reverse converter for the low cost moduli base {2n -1,2n ,2n+1} . The moduli of this type allow for the memoryless reverse conversion using the Chinese Remainder Theorem because the orthogonal projections can be obtained by shifts and additions. Moreover, the modulo reduction of the sum of projections and sign detection algorithms are shown. Also the converter architecture is presented.
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