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1

Evaluation of Sustainable Development in the Member States of the European Union

Bujanowicz-Haraś B., Janulewicz P., Nowak A., Krukowski A.

Problemy Ekorozwoju

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2015

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Vol. 10, nr 2

71--78

EN

This study evaluates the level of sustainable development in 28 member states of the European Union in 2011-2013. Research was carried out based on the so-called Hellwig’s development model method, which enabled the construction of a synthetic measure of sustainable development. It is based on indicators related to economic, social and environmental governance, as used in the European Union. The adopted method made it possible to evaluate the studied phenomenon as a whole, providing grounds for assigning the member states into four uniform groups characterised by a similar level of development. Group I, showing the highest level of sustainable development, comprised Sweden, Luxembourg, Slovenia, Denmark, Austria, and Finland. Conversely, Portugal, Bulgaria, Romania and Hungary were assigned to group IV.

PL

W opracowaniu dokonano oceny poziomu rozwoju zrównoważonego w 28 krajach członkowskich Unii Europejskiej w latach 2011-2013. Badania przeprowadzono w oparciu o metodę tzw. wzorca rozwoju Hellwiga, która umożliwiła skonstruowanie syntetycznego miernika rozwoju zrównoważonego. Bazuje on na stosowanych w Unii Europejskiej wskaźnikach, dotyczących ładu gospodarczego, społecznego oraz środowiskowego. Zastosowana metoda pozwoliła na kompleksową ocenę badanego zjawiska, dając podstawę do podziału krajów członkowskich na cztery jednorodne grupy charakteryzujące się podobnym poziomem rozwoju. Do grupy I, o najwyższym poziomie rozwoju zrównoważonego zaklasyfikowano Szwecję, Luksemburg, Słowenię, Danię, Austrię i Finlandię. W grupie IV znalazły się natomiast Portugalia, Bułgaria, Rumunia i Węgry.

2

An insight a digital sensor for delta-sigma modulator investigation

Hejn K., Krukowski A.

Prace Przemysłowego Instytutu Elektroniki

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1998

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nr 132

58-61

EN

Even an ideal delta-sigma modulator exhibits certain nonlinear behaviour. So its comprehensive analytical description has been both an absorbing and confusing task. Hence simulation and measurement are the key factor for a successful evaluation of the delta-sigma structure. This work is about high-quality decimation filters (digital sensors) for delta-sigma modulator investigations. They are based on a two-phase (two-branch) parallel structure using recursive allpasses which are particularly suitable for decimation by a factor of two. Moreover the repeated use of a basic decimation stage (BDS) makes this structure highly modular and well fittted for silicon implementation. An important BDS with only three coefficients (1/8, 9/16 and -1/16) has been presented in detail. Applied in the five stage decimaior and compatible with CMOS technology, it achieves a 20-bit processing accuracy for the passband of 20 kHz -without the design complexity and cost penalties incurred in alternative approaches. The paper includes some design results with performance evaluation under fixed point arithmetic. The in-situ developed software tools are also described.

3

A design technique for polyphase decimators with binary constrained coefficients for high resolution A/D converters

Krukowski A., Kale I., Morling R., Hejn K.

Prace Przemysłowego Instytutu Elektroniki

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1998

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nr 132

53-56

EN

This paper presents a design technique for liigh fidelity multistage decimation filters based on the polyphase and decimator structures presented in [1][2], catering for powers of two sample-rate decreases. The technique is well suited for Analog-to-Digital Converter (ADC) applications in excess of 16 bit resolution. The resulting filter coefficients are constrained to the required bit length using a "bit tipping algorithm" [3]. This technique is comparatively presented through an example of a cascaded decimation filter, designed for a 20-bit resolution ADC and compared to with other approximation methods. The coefficients and frequency responses of the cascaded filler are reported.

4

A "bit-flipping" approach to multistage two-path decimation filter design

Krukowski A., Kale I., Cain G., Hejn K.

Prace Przemysłowego Instytutu Elektroniki

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1998

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nr 132

42-51

EN

This paper presents a design technique for high fidelity multistage decimation filters based on the polyphase decimator structures presented by Constantinides et al, catering for powers of two sample-rate decreases. The technique is well suited for Analog-to-Digital Convener (ADC) applications in excess of 16-bit resolution. The resulting filter coefficients are constrained to the required bit length using a "bit-flipping algorithm" This technique illustrated in the context of an example of a cascaded decimation filter, designed for a 20-bit resolution ADC. and compared to other approximation methods. The resulting coefficient values and frequency responses of the cascaded filters are reported