Wyniki wyszukiwania - BazTech

1

A 400 fJ per-cycle frequency reference for internet of things

Coustans M., Krummenacher F., Terrier C., Kayal M.

International Journal of Microelectronics and Computer Science

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2016

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Vol. 7, nr 2

41--46

EN

This work presents an ultra-low power oscillator designed to target different contexts, such as crystal-assisted timekeeping, reference oscillator to optimize the always on domain of a microcontroller or wake-up timer. This oscillator enables ultralow power operation in 0.18 μm CMOS technology; the core oscillator consumes 2.5 nW at room temperature, with a temperature stability of 14 ppm/°C [-40°C - 60°C] and 0.07 %/V supply sensitivity.

2

Design considerations for an 8-decade current-to-digital converter with fA sensitivity

Voulgari E., Noy M., Anghinolfi F., Perrin D., Krummenacher F., Kayal M.

International Journal of Microelectronics and Computer Science

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2015

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Vol. 6, nr 3

79--85

EN

Radiation measurements for high energy physics experiments, nuclear facilities, hospitals and hadron therapy institutes require precise low current sensing. This paper provides a methodology for experimental characterisation of the leakage current sources present at the input of a current-to-digital converter. The limitations in sub-picoampere current measurements are presented along with the design of an ASIC that can accurately measure currents in the femto-ampere range after integrating over sufficient time. Proposals to minimise the subthreshold leakage current of the switches connected to the input, the leakage current of the package, the leakage of the PCB and the leakage related to the ESD protection diodes are shown. The remaining leakage current can be measured and subtracted. The front-end can digitise currents over 8 decades produced by a radiation detector. These guidelines were established during the current design and testing and will be used for the second version of the front-end electronics that will be installed at CERN for radiation protection and monitoring.

3

Design and Noise Analysis of a Novel Auto-Zeroing Structure for Continuous-Time Instrumentation Amplifiers

Maréchal S., Nys O., Krummenacher F., Chevroulet M., Kayal M.

International Journal of Electronics and Telecommunications

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2013

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Vol. 59, No. 4

397-404

EN

This paper introduces a low-noise, low-power amplifier for high-impedance sensors. An innovative circuit using an auto-zeroed architecture combined with frequency modulation to reject offset and low-frequency noise is proposed and analysed. Special care was given to avoid broadband noise aliasing and chopping in the signal path, and to minimize both the resulting equivalent input offset voltage and equivalent input biasing current. The theoretical noise analysis of the proposed topology covers most of the noise sources of the circuit. Simulations show that the input-referred noise level of the circuit is 13.4nV/√Hz for a power consumption of 85µA with a power supply from 1.8V to 3.6V.

4

Compact Modelling of Ultra Deep Submicron CMOS Devices

Grabiński W., Sallese J.M., Bucher M., Krummenacher F.

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2002

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Vol. 50, Nr 1

13--27

EN

The technology of CMOS very large-scale integrated circuits (VLSI) has achieved remarkable advances over last 25 years and the progress is expected to continue well into this century. However, even before the minimum feature sizes of the active VLSI devices reach the fundamental limits, this evolution is expected to encounter severe technological and economic problems when the dimensions go below sub-quarter micron, the so called ultra deep submicron (UDSM). There are many physical effects that need to be addressed while modelling UDSM devices , such as quantization of the inversion layer, mobility degradation, carrier velocity saturation and overshoot, polydepletion effects. In this paper, the advances in compact MOSFET devices will be illustrated using application examples of the EPEL-EKV model.

5

Advanced compact modeling of the deep submicron technologies

Grabiński W., Bucher M., Sallese J.-M., Krummenacher F.

Journal of Telecommunications and Information Technology

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2000

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nr 3-4

31-42

EN

The technology of CMOS large-scale integrated circuits (LSI's) achieved remarkable advances over last 25 year and the progress is expected to continue well into the next century. The progress has been driven by the downsizing of the active devices such as MOSFETs. Approaching these dimensions, MOSFET characteristics cannot be accurately predicted using classical modeling methods currently used in the most common MOSFET models such as BSIM, MM9 etc, without introducing large number of empirical parameters. Various physical effects that needed to be considered while modeling UDSM devices: quantization of the inversion layer, mobility degradation, carrier velocity saturation and overshoot, polydepletion effects, bias dependent source/drain resistances and capacitances, vertical and lateral doping profiles, etc. In this paper, we will discuss the progress in the CMOS technology and the anticipated difficulties of the sub-0.25 žm LSI downsizing. Subsequently, basic MOSFET modeling methodologies that are more appropriate for UDSM MOSFETs will be presented as well. The advances in compact MOSFET devices will be illustrated using application examples of the EPFL EKV model