A cascaded H-bridge (CHB) multilevel inverter generally requires several DC sources. An alternative option is to replace the separate DC source feeding an H-bridge cell with a capacitor, while maintaining the other H-bridge cell with a real DC voltage source. In this paper a 7-level cascaded H-bridge inverter with a single DC-source is presented. This paper focuses mainly to achieve effective capacitor voltage balancing and selective harmonic elimination (SHE) based on the Newton Raphson algorithm (N–R). It shows hope to reduce the voltage ripple of the capacitors, which leads to higher power conversion efficiency with equal power distribution, reduces the initial cost, and complexity hence it is apt for industrial applications. Simulation results support the proposed control technique.
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Conventionally, control signals fed to the PWM inverters are produced by electronic hardware or microprocessor. The cost and complexity of hardware implementation are considerable and control algorithms differ for PWM for different levels and topologies is proposed. On-line computation in the microprocessor approach is laborious and time-consuming. These two approaches seem impractical when they are applied to PWM multilevel inverter control. In this paper, programmed matrix PWM based on two dimensional addressing modes for FPGA memories can solve the problems mentioned above and provides easy, fast and steady control. Experimental results are carried out to confirm the high performance of the proposed embedded PWM.
PL
W artykule zaproponowano programowalny macierzowy przekształtnik PWM bazujący na dwuwymiarowym adresowaniu pamięci FPGA. Otrzymano wbudowany moduł PWM znacznie prostszy od typowych rozwiazań.
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