High-density electroencephalographic (EEG) systems are utilized in the study of the human brain and its underlying behaviors. However, working with EEG data requires a well-cleaned signal, which is often achieved through the use of independent component analysis (ICA) methods. The calculation time for these types of algorithms is the longer the more data we have. This article presents a hybrid implementation of the fastICA algorithm that uses parallel programming techniques (libraries and extensions of the Intel processors and CUDA programming), which results in a significant acceleration of execution time on selected architectures.
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Objectives: The electroencephalographic signal is largely exposed to external disturbances. Therefore, an important element of its processing is its thorough cleaning. Methods: One of the common methods of signal improvement is the independent component analysis (ICA). However, it is a computationally expensive algorithm, hence methods are needed to decrease its execution time. One of the ICA algorithms (fastICA) and parallel computing on the CPU and GPU was used to reduce the algorithm execution time. Results: This paper presents the results of study on the implementation of fastICA, which uses some multi-core architecture and the GPU computation capabilities. Conclusions: The use of such a hybrid approach shortens the execution time of the algorithm.
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W artykule przedstawiono opis hybrydowego systemu obliczeniowego, który został uruchomiony w Laboratorium sieciowych systemów audiowizualnych Centrum Informatyzacji i Bezpieczeństwa Transportu utworzonego przez Wyższą Szkołę Ekonomii i Innowacji w Lublinie. Omówiono architekturę systemu oraz podstawowe założenia dotyczące tworzenia efektywnych programów równoległych w architekturze CUDA oraz standardzie OpenCL.
EN
The article describes a hybrid computing system, which was launched at the laboratory for networked audiovisual systems at the Centre for IT and Safety of Transportation created by the College of Economy and Innovation in Lublin. The paper discusses the system architecture and basic assumptions related to the design of efficient parallel programs in CUDA architecture and OpenCL standard.
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