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Technology mapping oriented to adaptive logic modules

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This paper presents an innovative method of technology mapping of the circuits in ALM appearing in FPGA devices by Intel. The essence of the idea is based on using triangle tables that are connected with different configurations of blocks. The innovation of the proposed method focuses on the possibility of choosing an appropriate configuration of an ALM block, which is connected with choosing an appropriate decomposition path. The effectiveness of the proposed technique of technology mapping is proved by experiments conducted on combinational and sequential circuits.
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Bibliogr. 27 poz., rys., tab.
  • Institute of Electronics, Silesian University of Technology, ul. Akademicka 2A, 44-100 Gliwice, Poland
  • Institute of Electronics, Silesian University of Technology, ul. Akademicka 2A, 44-100 Gliwice, Poland
  • [1] S.B. Akers, “Binary decision diagrams”, IEEE Transactions on Computers, C 27(6), 509‒516 (1978).
  • [2] R.L. Ashenhurst, “The decomposition of switching functions”, Proceedings of the International Symposium on the Theory of Switching, 1957.
  • [3] Berkeley Logic Synthesis Group: ABC: A System f or Sequential Synthesis And VerificAtion, Dec. 2005 [Online]. Available:
  • [4] J.A. Brzozowski and T. Łuba: Decomposition of Boolean Functions Specified by Cubes, Journal of Multi Valued Logic & Soft Computing, vol. 9, pp. 377‒417, Old City Publishing Inc., Philadelphia 2003.
  • [5] D. Chen and J. Cong, “DAOmap: A depth optimal area optimization mapping algorithm”, in Proc. ICCAD,pp. 752‒759, (2004).
  • [6] Collaborative Benchmarking Laboratory, Department of Computer Science at North Carolina State University, http://www.cbl.ncsu/edu/.
  • [7] H.A. Curtis, The Design of Switching Circuits, D. van Nostrand Company, Inc., Princeton, New Jersey, Toronto, New York, 1962.
  • [8] E. Dubrova, “A polynominal time algorithm for non disjoint decomposition of multi valued functions”, 34th International Symposium on Multiple-Valued Logic,309‒314 (2004).
  • [9] I. Háleček, P. Fišer, and J. Schmidt, “Towards AND/XOR balanced synthesis: Logic circuits rewriting with XOR”, Microelectronics ReliAbility, 81, 274‒286 (2018)
  • [10] Intel Stratix 10 Logic Array Blocks and Adaptive Logic Modules User Guide, UG-S10LAB, 2017.
  • [11] S. Jang, B. Chan, K. Chung, and A. Mishchenko, “WireMap: FPGA technology mapping for improved routability and enhanced LUT merging”, ACM Trans. Reconfigurable Technology and Systems (TRETS),2(2), Article 14 (2009).
  • [12] M. Kubica and D. Kania, “SMTBDD : new form of BDD for logic synthesis”, International Journal of Electronics and Tele-communications,62(1), 33‒41 (2016).
  • [13] M. Kubica and D. Kania, “Area oriented technology mapping for LUT based logic blocks”, International Journal of Applied Mathematics and Computer Science,27 (1), 207‒222 (2017).
  • [14] M. Kubica and D. Kania, “Decomposition of multi output functions oriented to configurability of logic blocks”, Bull. of the Pol. Ac.: Tech. 65(3) 317‒331 (2017).
  • [15] M. Kubica, A. Opara, and D. Kania, “Logic synthesis for FPGAs based on cutting of BDD, Microprocessor and Microsystems”, 52, 173‒187 (2017).
  • [16] Y T. Lai, M. Pedram, and S. Vrudhula, “BDD based decomposition of logic for functions with applications to FPGA synthesis”, in Proc. of Design Automation Conf., pp. 642‒647, 1993.
  • [17] T. Łuba, G. Borowik, and A. Kraśniewski, “Synthesis of finite state machines for implementation with programmable structures”, Electronics and Telecommunications Quarterly,55/2009 (2), 183‒200 (2009).
  • [18] S. Minato, Binary Decision Diagrams and Applications f or VLSI CAD, Kluwer Academic Publishers, 1996.
  • [19] A. Mishchenko, R. Brayton, W. Feng, and J. Greene, “Technology mapping into general programmable cells”, Proc. FPGA’15.
  • [20] A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton, “Com-binational and sequential mapping with priority cuts”, in Proceedings of the 3007 IEEE/ACM International Conference on Computer-Aided Design (ICCAD ‘07), 354‒361, 2007.
  • [21] A. Mishchenko, S. Chatterjee, and R. Brayton, “Improvements to technology mapping for LUT based FPGAs”, IEEE TCAD, 26(2), 240‒253, 2007.
  • [22] A. Opara, M. Kubica, and D. Kania, “Strategy of logic synthesis using MTBDD dedicated to FPGA”, Integration: The VLSI Journal 62, 142‒158 (2018).
  • [23] S. Ray et al., “Mapping into LUT structures” in Design, Automation and Test in Europe, Dresden, Germany, pp. 1579‒1584, 2012.
  • [24] C. Scholl, Functional Decomposition with Application to FPGA Synthesis,Kluwer Academic Publisher, Boston, 2001.
  • [25] P. Szotkowski, M. Rawski, and H. Selvaraj, “A graph based approach to symbolic functional decomposition of finite state machines”, Systems Science, 35 (2), 41‒47, 2009.
  • [26] N. Vemuri, P. Kalla, and R. Tessier, BDD based logic synthesis for LUT-based FPGAs, ACM Trans. Design Autom. Electron. Syst.,7 (4), 501‒525 (2002).
  • [27] C. Yang and M. Ciesielski, “BDS: A BDD based logic optimization system”, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.,21 (7), 866‒876 (2002).
Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2020).
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