Area equivalent WKB Compact modeling approach for tunneling probability in Hetero-Junction TFETs including ambipolar behaviour

• Autorzy: Horst Fabian , Farokhnejad Atieh , Darbandy Ghader , Iñíguez Benjamín , Kloes Alexander
• Języki publikacji: EN

Abstrakty

EN

This paper introduces an innovative modeling approach for calculating the band-to-band (B2B) tunneling probability in tunnel-field effect transistors (TFETs). The field of application is the usage in TFET compact models. Looking at a tunneling process in TFETs, carriers try to tunnel through an energy barrier which is defined by the device band diagram. The tunneling energy barrier is approximated by an approach which assumes an area equivalent (AE) triangular shaped energy profile. The simplified energy triangle is suitable to be used in the Wentzel-Kramers-Brillouin (WKB) approximation. Referring to the area instead of the electric field at individual points is shown to be a more robust approach in terms of numerical stability. The derived AE approach is implemented in an existing compact model for double-gate (DG) TFETs. In order to verify and show the numerical stability of this approach, modeling results are compared to TCAD Sentaurus simulation data for various sets of device parameters, whereby the simulations include both ON- and AMBIPOLAR-state of the TFET. In addition to the various device dimensions, the source material is also changed to demonstrate the feasibility of simulating hetero-junctions. Comparing the modeling approach with TCAD data shows a good match. Apart the limitations demonstrated and discussed in this paper, the main advantage of the AE approach is the simplicity and a better fit to TCAD data in comparison to the quasi-2D WKB approach.

Słowa kluczowe

EN

TFET; tunneling probability; WKB approximation; heterojunction; compact modeling; closed-form; double-gate; DG; ambipolarity

PL

TFET; modelowanie kompaktowe; dwubiegunowość

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2018
• Tom: Vol. 9, nr 2
• Strony: 47--59
• Opis fizyczny: Bibliogr. 19 poz.

Twórcy

autor

Horst Fabian

• NanoP, TH Mittelhessen University of Applied Sciences, 35390 Giessen, Germany

autor

Farokhnejad Atieh

• NanoP, TH Mittelhessen University of Applied Sciences, 35390 Giessen, Germany

autor

Darbandy Ghader

• NanoP, TH Mittelhessen University of Applied Sciences, 35390 Giessen, Germany

autor

Iñíguez Benjamín

• Universitat Rovira i Virgili, 43007 Tarragona, Spain

autor

Kloes Alexander

• NanoP, TH Mittelhessen University of Applied Sciences, 35390 Giessen, Germany

Bibliografia

• [1] B. Razavi, Design of Analog CMOS Integrated Circuits. New York, NY 10020, USA: Tata McGraw-Hill, 2001.
• [2] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.- S. P. Wong, “Device scaling limits of Si MOSFETs and their application dependencies,” Proceedings of the IEEE, vol. 89, no. 3, pp. 259-288, Mar. 2001.
• [3] A. C. Seabaugh and Q. Zhang, “Low-voltage tunnel transistors for beyond CMOS logic,” Proceedings of the IEEE, vol. 98, no. 12, pp. 2095-2110, Dec. 2010.
• [4] H. Lu and A. Seabaugh, “Tunnel field-effect transistors: State-of-theart,” IEEE Journal of the Electron Devices Society, vol. 2, no. 4, pp. 44-49, Jul. 2014.
• [5] A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy efficient electronic switches,” Nature, vol. 479, no. 7373, pp. 329-337, Nov. 2011.
• [6] S. M. Sze and K. K. Ng, Physics of semiconductor devices, 3rd ed. Hoboken, New Jersey, USA: John Wiley & Sons, Inc., 2007.
• [7] A. Gehring, “Simulation of tunneling in semiconductor devices,” Ph.D. dissertation, Technische Universität Wien, Austria, 2003.
• [8] F. Horst, A. Farokhnejad, Q. Zhao, B. Iñíguez, and A. Kloes, “2-D physics-based compact DC modeling of double-gate tunnel-FETs,” IEEE Transactions on Electron Devices, pp. 1-7, Jul. 2018.
• [9] M. Graef, T. Holtij, F. Hain, A. Kloes, and B. Iñíguez, “A 2D closed form model for the electrostatics in hetero-junction double-gate tunnel-FETs for calculation of band-to-band tunneling current,” Microelectronics Journal, vol. 45, no. 9, pp. 1144-1153, Sep. 2014.
• [10] F. Horst, M. Graef, F. Hosenfeld, A. Farokhnejad, F. Hain, G. V. Luong, Q.-T. Zhao, B. Iñíguez, and A. Kloes, “Implementation of a DC compact model for double-gate Tunnel-FET based on 2D calculations and application in circuit simulation,” in 2016 46th European Solid-State Device Research Conference (ESSDERC). IEEE, Sep. 2016, pp. 456-459.
• [11] M. Graef, T. Holtij, F. Hain, A. Kloes, and B. Iñíguez, “Improved analytical potential modeling in double-gate tunnel-FETs,” in 2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES). IEEE, Jun. 2014, pp. 49-53.
• [12] L. Zhang and M. Chan, “SPICE modeling of double-gate tunnel-FETs including channel transports,” IEEE Transactions on Electron Devices, vol. 61, no. 2, pp. 300-307, Feb. 2014.
• [13] J. Slotboom and H. De Graaff, “Measurements of bandgap narrowing in Si bipolar transistors,” Solid-State Electronics, vol. 19, no. 10, pp. 857-862, Oct. 1976.
• [14] J. del Alamo, S. Swirhun, and R. M. Swanson, “Simultaneous measurement of hole lifetime, hole mobility and bandgap narrowing in heavily doped n-type silicon,” in 1985 International Electron Devices Meeting. IEEE, Dec. 1985, pp. 290-293.
• [15] R. Tsu and L. Esaki, “Tunneling in a finite superlattice,” Appl. Phys. Lett., vol. 22, no. 11, pp. 562-564, Jun. 1973.
• [16] C. B. Duke, Tunneling in solids. Academic Press, 1969, vol. 10.
• [17] M. Schwarz, T. Holtij, A. Kloes, and B. Iñíguez, “Complex 2D electric field solution in undoped double-gate MOSFETs,” IETE Journal of Research, vol. 58, no. 3, pp. 197-204, Sep. 2012.
• [18] F. Horst, A. Parokhnejad, B. Iñíguez, and A. Kloes, “An area equivalent WKB approach to calculate the b2b tunneling probability for a numerical robust implementation in TFET compact models,” in 2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES). IEEE, Jun. 2018, pp. 45-50.
• [19] Synopsys Inc., TCAD Sentaurus Device User Guide, 2012, Version G-2012.06.

Uwagi

Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2019).