Hardware-Efficient Schemes of Quaternion Multiplying Units for 2D Discrete Quaternion Fourier Transform Processors

• Autorzy: Cariow A. , Cariowa G. , Chicheva M.
• Języki publikacji: EN

Abstrakty

EN

In this paper, we offer and discuss three efficient structural solutions for the hardware-oriented implementation of discrete quaternion Fourier transform basic operations with reduced implementation complexities. The first solution – a scheme for calculating sq product, the second solution – a scheme for calculating qt product, and the third solution – a scheme for calculating sqt product, where s is a so-called i -quaternion, t is an j - quaternion, and q – is an usual quaternion. The direct multiplication of two usual quaternions requires 16 real multiplications (or two-operand multipliers in the case of fully parallel hardware implementation) and 12 real additions (or binary adders). At the same time, our solutions allow to design the computation units, which consume only 6 multipliers plus 6 two input adders for implementation of sq or qt basic operations and 9 binary multipliers plus 6 two-input adders and 4 four-input adders for implementation of sqt basic operation.

Słowa kluczowe

EN

discrete quaternion Fourier transform; fast algorithms; implementation complexity reduction; FPGA implementation

• Wydawca: Wydawnictwo PAK
• Czasopismo: Measurement Automation Monitoring
• Rocznik: 2017
• Tom: Vol. 63, No. 6
• Strony: 206--208
• Opis fizyczny: Bibliogr. 17 poz., rys., wzory

Twórcy

autor

Cariow A.

• West Pomieranian University of Technology, 49 Żołnierska St., 71-210 Szczecin, Poland

autor

Cariowa G.

• West Pomieranian University of Technology, 49 Żołnierska St., 71-210 Szczecin, Poland

autor

Chicheva M.

• Samara University, 34 Moskovskoye sh., 443086 Samara, Russia
• IPSI RAS – Branch of the FSRC “Crystallography and Photonics”, 151, 443001 Samara, Russia

Bibliografia

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Uwagi

PL

Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę (zadania 2017).