FPGA implementation of reverse residue conversion based on the new Chinese Remainder Theorem II- Part II: experimental results

• Autorzy: Ulman Z. , Czyżak M. , Smyk R.
• Konferencja: Computer Applications in Electrical Engineering 2012 (23-24.04.2012; Poznań, Polska)

Abstrakty

EN

This work describes a hardware realization of the converter of numbers from the Residue Number System (RNS) to the binary system. The converter is based on the new form of the Chinese Remainder Theorem (CRT) termed the New CRT II. The theoretical aspects of conversion by this method have been described in Part I. The implementation of the converter has been carried out in the Xilinx FPGA environment. The general architecture of the system is shown, also the realizations of the selected blocks of the converter are described. The hardware amount and attainable pipelining rate are given. The converter has been realized for the RNS base composed of eight 5-bit moduli that gives the dynamic range of about 37 bits.

Słowa kluczowe

EN

FPGA; Residue Number System; RNS; Chinese remainder theorem; CRT; New CRT II

• Wydawca: Wydawnictwo Politechniki Poznańskiej
• Czasopismo: Poznan University of Technology Academic Journals. Electrical Engineering
• Rocznik: 2012
• Tom: No. 71
• Strony: 139--147
• Opis fizyczny: Bibliogr. 17 poz., rys., tab.

Twórcy

autor

Ulman Z.

• Gdansk University of Technology

autor

Czyżak M.

• Gdansk University of Technology

autor

Smyk R.

• Gdansk University of Technology

Bibliografia

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