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Performance evaluation of the MSMPS algorithm under different distribution traffic

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Języki publikacji
EN
Abstrakty
EN
In this paper, the Maximal Size Matching with Permanent Selection (MSMPS) scheduling algorithm and its performance evaluation, under different traffic models, are described. In this article, computer simulation results under nonuniformly, diagonally and lin-diagonally distributed traffic models are presented. The simulations was performed for different switch sizes: 4×4, 8×8 and 16×16. Results for MSMPS algorithm and for other algorithms well known in the literature are discussed. All results are presented for 16×16 switch size but simulation results are representative for other switch sizes. Mean Time Delay and efficiency were compared and considered. It is shown that our algorithm achieve similar performance results like another algorithms, but it does not need any additional calculations. This information causes that MSMPS algorithm can be easily implemented in hardware.
Rocznik
Tom
Strony
74--79
Opis fizyczny
Bibliogr. 17 poz., rys., tab.
Twórcy
  • Chair of Communication and Computer Networks, Faculty of Electronics and Telecommunications, Poznan University of Technology, Polanka st 3, 60-965 Poznan, Poland
autor
  • Chair of Communication and Computer Networks, Faculty of Electronics and Telecommunications, Poznan University of Technology, Polanka st 3, 60-965 Poznan, Poland
Bibliografia
  • [1] N. McKeown, “The iSLIP scheduling algorithm for input-queued switches”, IEEE/ACM Trans. Netw., vol. 7, pp. 188–200, 1999.
  • [2] A. Baranowska and W. Kabaciński, “The new packet scheduling al- gorithms for VOQ switches”, in Telecommunications and Networking – ICT 2004, J. Neuman de Souza, P. Dini, and P. Lorenz, Eds. LNCS 3124, pp. 711–716. Springer, 2004.
  • [3] A. Baranowska and W. Kabaciński, “MMRS and MMRRS packet scheduling algorithms for VOQ switches”, in Proc. MMB & PGTS 2004 – 12th GI/ITG Conf. Measur. Eval. Comp. Commun. Sys. (MMB) & 3rd Polish-German Teletr. Symp. (PGTS), Dresden, Germany, 2004.
  • [4] A. Baranowska and W. Kabaciński, “Evaluation of MMRS and MMRRS packet scheduling algorithms for VOQ switches under bursty packet arrivals”, in Proc. Worksh. High Perfor. Switch. Rout. HPSR 2005, Hong Kong, China, 2005, pp. 327–331.
  • [5] A. Baranowska and W. Kabaciński, “Hierarchical round-robin matching for virtual output queuing switches”, in Proc. Adv. Industr. Conf. Telecommun. AICT 2005, Lisbon, Portugal, 2005, pp. 196–201.
  • [6] T. Anderson et al., “High-speed switch scheduling for local-area networks”, ACM Trans. Comp. Sys., vol. 11, no. 4, pp. 319–352, 1993.
  • [7] G. Danilewicz and M. Dziuba, “The new MSMPS packet scheduling algorithm for VOQ switches”, in Proc. 8th IEEE, IET Int. Symp. Commun. Sys. Netw. Digit. Sig. Process. CSNDSP 2012, Poznań, Poland, 2012.
  • [8] Y. Tamir and G. Frazier, “High performance multiqueue buffers for VLSI communication switches”, in Proc. 15th Ann. Int. Symp. Comp. architec. ISCA 1988, Honolulu, Hawaii, USA, 1988, pp. 343–354.
  • [9] Myung-Ki Shin, Ki-Hyuk Nam, and Hyoung-Jun Kim, Software-defined networking (SDN): A reference architecture and open APIs, in Proc. Int. Conf. ICT Converg. ICTC 2012, Jeju, Korea, 2012.
  • [10] A. Baranowska and W. Kabaciński, “Hierarchiczny algorytm planowania przesyłania pakietów dla przełącznika z VOQ”, in Poznańskie Warsztaty Telekomunikacyjne PWT 2004, Poznań, Poland, 2004 (in Polish).
  • [11] H. Jonathan Chao and B. Liu, High Performance Switches and Routers. New Jersey: Wiley, 2007, pp. 195–197.
  • [12] P. Giaccone, D. Shah, and S. Prabhakar, “An implementable parallel scheduler for input-queued switches”, IEEE Micro, vol. 22, no. 1, pp. 19–25, 2002.
  • [13] K. Yoshigoe and K. J. Christensen, “An evolution to crossbar switches with virtual ouptut queuing and buffered cross points”, IEEE Network, vol. 17, no. 5, pp. 48–56, 2003.
  • [14] D. Shah, P. Giaccone, and B. Prabhakar, “Efficent randomized algorithms for input-queued switch scheduling”, IEEE Micro, vol. 22, no. 1, pp. 10–18, 2002.
  • [15] P. Giaccone, B. Prabhakar, and D. Shah, “Randomized scheduling algorithms for high-aggregate bandwidth switches”, IEEE J. Selec. Areas Commun., vol. 21, no. 4, pp. 546–559, 2003.
  • [16] Y. Jiang and M. Hamdi, “A fully desynchronized round-robin matching scheduler for a VOQ packet switch architecture”, in Proc. IEEE Worksh. High Perform. Switch. Routing HPSR 2001, Dallas, TX, USA, 2001, pp. 407–411.
  • [17] A. Bianco, P. Giaccone, E. Leonardi, and F. Neri, “A framework for differential frame-based matching algorithms in input-queued switches”, in Proc. 23rd Ann. Joint Conf. IEEE Comp. Commun. Soc. IEEE INFOCOM 2004, Hong Kong, China, 2004.
Typ dokumentu
Bibliografia
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