PL EN


Preferencje help
Widoczny [Schowaj] Abstrakt
Liczba wyników
Tytuł artykułu

Pt/Al2O3/HfO2/Ti/TiN bi-layer RRAM device for imply–inhibit logic applications: Unveiling the resistive potential by experiment and simulation

Identyfikatory
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
Aluminum oxide (Al2O3)/hafnium oxide (HfO2) bi-layer resistive random access memory (RRAM) was fabricated by atomic layer deposition and sputtering method with a titanium (Ti)/titanium nitride (TiN) top electrode and a platinum (Pt) bottom electrode to achieve optimized performance. High-resolution transmission electron microscopy results clearly show the cross-sectional nanostructure of the Pt/Al2O3/HfO2/Ti/TiN RRAM devices. Examination of the X-ray photoelectron spectroscopy depth profile and X-ray diffraction peaks revealed the bonding state and presence of the proposed bi-layer structure. The device features a forming-free function with a stable resistance ratio (∼10) of ON/OFF states, low SET and RESET voltages, switching duration of up to 103 cycles, and longer data retention. The current–voltage characteristics of the proposed RRAM device implemented with the VTEAM simulation package and its performance with respect to the experimental results were studied. In addition, imply–inhibit logic gates were developed, and their performance was studied. The results show that the proposed imply–inhibit logic has significant advantages over typical CMOS logic in terms of performance, delay, and device count.
Wydawca
Rocznik
Strony
196--209
Opis fizyczny
Bibliogr. 28 poz., rys., tab.
Twórcy
  • Department of Electrical and Electronics Engineering, Kumaraguru College of Technology Coimbatore-641049, India
  • Department of Electrical and Electronics Engineering, Kumaraguru College of Technology Coimbatore-641049, India
Bibliografia
  • [1] Tan, T., Du, Y., Cao, A., Sun, Y., Zhang, H., Zha, G., Resistive switching of the HfOX/HfO2 bi-layer heterostructure and its transmission characteristics as a synapse, RSC Adv., 2018, 8: 41884–41891. doi: 10.1039/C8RA06230G
  • [2] Zahoor, F., Azni, T.Z., Zulkifli, Khanday, F.A., Resistive random access memory (RRAM): an overview of materials switching mechanism performance multilevel cell (MLC) storage modeling and applications, Nanoscale Res. Lett., 2020, 15: 90. doi: 10.1186/s11671-020-03299-9
  • [3] Ielmini, D., Resistive switching memories based on metal oxides: mechanisms reliability and scaling, Semicond. Sci. Technol., 2016, 31: 063002. doi: 10.1088/0268-1242/31/6/063002
  • [4] Huang, C.Y., Jieng, J.H., Jang, W.Y., Lin, C.H., Tseng, T.Y., Improved resistive switching characteristics by Al2O3 layers inclusion in HfO2-based RRAM devices, ECS Solid. State Lett., 2013, 2: P63. doi: 10.1149/2.006308ssl
  • [5] Park, S., Cho, K., Jung, J., Kim, S., Annealing effect of Al2O3 tunnel barriers in HfO2-based ReRAM devices on nonlinear resistive switching characteristics, J. Nanosci. Nanotechnol., 2015, 15: 7569−7572. doi: 10.1166/jnn.2015.11138
  • [6] Ambrosi, E., Bricalli, A., Laudato, M., Ielmini, D., Impact of oxide and electrode materials on the switching characteristics of oxide ReRAM devices, Faraday Discuss., 2019, 213: 87–98. doi: 10.1039/C8FD00106E
  • [7] Patel, Y.D., Treated HfO2 based RRAM devices with ru, tan, tin as top electrode for in-memory computing hardware, Master Thesis, New Jersey Institute of Technology, New Jersey, 2020, 1807. https://digitalcommons.njit.edu/theses/1807
  • [8] Arun, N., Nageswara Rao, S.V.S., Pathak, A.P., Effects of bottom electrode materials on the resistive switching characteristics of HfO2-based RRAM devices, J. Electron. Mater., 2013, 52: 1541–1551. doi: 10.1007/s11664-022-10136-5
  • [9] Wright, J.T., Carbaugh, D.J., Haggerty, M.E., Richard, A.L., Ingram, D.C., Kaya, S., et al., Thermal oxidation of silicon in a residual oxygen atmosphere the RESOX process for self-limiting growth of thin silicon dioxide films, Semicond. Sci. Technol., 2016, 31: 105007 10.1088/0268-1242/31/10/105007
  • [10] Aarik, L., Piller, C.T., Raud, J., Talviste, R., Jõgi, I., Aarik, J., Atomic layer deposition of α-Al2O3 from trimethylaluminum and H2O: Effect of process parameters and plasma excitation on structure development, J. Cryst., 2023, 609: 127148. doi: 10.1016/j.jcrysgro.2023.12714
  • [11] Fang, Y., Improvement of HfOx-based RRAM device variation by inserting ALD TiN buffer layer, IEEE Electron. Device Lett., 2018, 39: 819–822. doi: 10.1109/LED.2018.2831698
  • [12] Yang, J.J., Pickett, M.D., Li, X., Ohlberg, D.A., Stewart, D.R., Williams, R.S., Memristive switching mechanism for metal/oxide/metal nanodevices, Nat. Nanotech., 2008, 3: 429–433. doi: 10.1038/nnano.2008.160
  • [13] Kvatinsky, S., Ramadan, M., Friedman, E.G., Kolodny, A., VTEAM: A general model for voltage-controlled memristors, IEEE Trans. Circuits Syst. II: Express Briefs., 2015, 62: 786–790. doi: 10.1109/TCSII.2015.2433536
  • [14] Bhullar, B.S., Gangacharyulu, D., Das, S.K., Temporal deterioration in thermal performance of screen mesh wick straight heat pipe using surfactant free aqueous nanofluids, Heat. Mass. Transf., 2017, 53: 241–251 10.1007/s00231-016-1785-6
  • [15] Kondaiah, P., Shaik, H., Mohan Rao, G., Studies on RF magnetron sputtered HfO2 thin films for microelectronic applications, Electron. Mater. Lett., 2015, 11: 592–600. doi: 10.1007/s13391-015-4490-6
  • [16] Wang, G., Qian, X., Cao, Y.Q., Cao, Z.Y., Fang, G.Y., Li, A.D., et al., Excellent resistive switching properties of atomic layer-deposited Al2O3/HfO2/Al2O3 trilayer structures for non-volatile memory applications, Nanoscale Res. Lett., 2015, 10: 135. doi: 10.1186/s11671-015-0846-y
  • [17] Athena, F.F., West, M.P., Hah, J., Hanus, R., Graham, S., Vogel, E.M., Towards a better understanding of the forming and resistive switching behavior of Ti-doped HfOx RRAM, J. Mater. Chem. C., 2022, 10: 5896. doi: 10.1039/D1TC04734E
  • [18] Napolean, A., Sivamangai, N.M., Naveen Kumar, R., Nithya, N., Electroforming atmospheric temperature and annealing effects on Pt/HfO2/TiO2/HfO2/Pt resistive random access memory cell, Silicon, 2022, 14: 2863. doi: 10.1007/s12633-021-01074-8
  • [19] Su, B., Cai, J., Zhang, Y., Wang, Y., Wang, S., et al., A 1T2M memristor-based logic circuit and its applications, Microelectron. J., 2023, 132: 105674. doi: 10.1016/j.mejo.2022.105674
  • [20] Xiaojuan, L., Chuanyang, S., Zeheng, T., Realization of complete boolean logic and combinational logic functionalities on a memristor-based universal logic circuit, Chin. J. Electron., 2024, 33: 1–10. doi: 10.23919/cje.2023.00.091
  • [21] Singh, T., Hybrid Memristor-CMOS (MeMOS) based logic gates and adder circuits, arXiv [cs.ET], 2015, 1506, 1–11. doi: 10.48550/arXiv.1506.06735
  • [22] Mandal, S., Sinha, J., Chakraborty, A., Design of Memristor – CMOS based logic gates and logic circuits. In 2nd International Conference on Innovations in Electronics, Signal Processing and Communication (IESC), Shillong, India, 2019, pp. 215–220. doi: 10.1109/IESPC.2019.8902355
  • [23] Kvatinsky, S., Satat, G., Wald, N., Friedman, E.G., Kolodny, A., Weiser, U.C., Memristor-based material implication (IMPLY) logic: Design principles and methodologies, IEEE Trans. VLSI Syst., 2014, 22: 2054–2066. doi: 10.1109/TVLSI.2013.2282132
  • [24] Mane, P.S., Paul, N., Behera, N., Sampath, M., Ramesha, C.K., Hybrid CMOS - Memristor based configurable logic block design. In International Conference on Electronics and Communication Systems (ICECS), Coimbatore, India, 2014, pp. 1–5. doi: 10.1109/ECS.2014.6892532
  • [25] Kvatinsky, S., Wald, N., Satat, G., Kolodny, A., Weiser, U.C., Friedman, E.G., MRL:, Memristor ratioed logic. In Proc. Int. Workshop on Cellular Nanoscale Network and Application, Turin, Italy, 2012, pp. 1–6. doi: 10.1109/CNNA.2012.6331426
  • [26] Hoffer, B., Rana, V., Menzel, S., Waser, R., Kvatinsky, S., Experimental demonstration of memristor-aided logic (MAGIC) using valence change memory (VCM), IEEE Trans. Electron. Devices, 2020, 67: 3115–3122. doi: 10.1109/TED.2020.3001247
  • [27] Ligang, G., Alibart, F., Strukov, D.B., Programmable CMOS/memristor threshold logic, IEEE Trans. Nanotechnol., 2013, 12: 115–119. doi: 10.1109/TNANO.2013.2241075
  • [28] Vourkasand, I., Sirakoulis, G.C., Memristor–based combinational circuits: A design methodology for encoders/decoders. Microelectron. J., 2014, 45: 59–70. doi: 10.1016/j.mejo.2013.10.001
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-f7e5b0a8-95cf-49b2-a6a1-63f8c08a4d39
JavaScript jest wyłączony w Twojej przeglądarce internetowej. Włącz go, a następnie odśwież stronę, aby móc w pełni z niej korzystać.