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The Impact of Noise and Mismatch on SAR ADCs and a Calibratable Capacitance Array Based Approach for High Resolutions

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Języki publikacji
EN
Abstrakty
EN
This paper describes widely used capacitor structures for charge-redistribution (CR) successive approximation register (SAR) based analog-to-digital converters (ADCs) and analyzes their linearity limitations due to kT/C noise, mismatch and parasitics. Results of mathematical considerations and statistical simulations are presented which show that most widespread dimensioning rules are overcritical. For high-resolution CR SAR ADCs in current CMOS technologies, matching of the capacitors, influenced by local mismatch and parasitics, is a limiting factor. For high-resolution medium-speed CR SAR ADCs, a novel capacitance array based approach using in-field calibration is proposed. This architecture promises a high resolution with small unit capacitances and without expensive factory calibration as laser trimming.
Twórcy
  • Integrated Analog Circuits and RF Systems Laboratory, RWTH Aachen University, Aachen, Germany
autor
  • Integrated Analog Circuits and RF Systems Laboratory, RWTH Aachen University, Aachen, Germany
autor
  • Integrated Analog Circuits and RF Systems Laboratory, RWTH Aachen University, Aachen, Germany
  • Integrated Analog Circuits and RF Systems Laboratory, RWTH Aachen University, Aachen, Germany
autor
  • Integrated Analog Circuits and RF Systems Laboratory, RWTH Aachen University, Aachen, Germany
Bibliografia
  • [1] J. L. McCreary and P. R. Gray, “All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques - Part I,” IEEE Journal of Solid-State Circuits, vol. 10, no. 6, pp. 371-379, Dec. 1975.
  • [2] M. Saberi, R. Lotfi, K. Mafinezhad, and W. A. Serdijn, “Analysis of Power Consumption and Linearity in Capacitive Digital-to-Analog Converters Used in Successive Approximation ADCs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, no. 8, pp. 1736-1748, Aug. 2011.
  • [3] S.-H. Cho, C.-K. Lee, J.-K. Kwon, and S.-T. Ryu, “A 550-uW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction,” IEEE Journal of Solid-State Circuits, vol. 46, no. 8, pp. 1881-1892, Aug. 2011.
  • [4] Y. Chang, C. Wang, and C. Wang, “A 8-bit 500 kS/s Low Power SAR ADC for Bio-Medical Applications,” in IEEE Asian Solid-State Circuits Conference, Nov. 2007, pp. 228-231.
  • [5] C. Liu, S. Chang, G. Huang, and Y. Lin, “hA 0.92mW 10-bit 50-MS/s SAR ADC in 0.13µm CMOS Process,” in Symposium on VLSI Circuits Digest of Technical Papers, Jun. 2009, pp. 236-237.
  • [6] V. Hariprasath, J. Guerber, S.-H. Lee, and U.-K. Moon, “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” Electronic Letters, vol. 46, no. 9, pp. 620-621, Apr. 2010.
  • [7] B. P. Ginsburg and A. P. Chandrakasan, “An Energy-Efficient Charge Recycling Approach for a SAR Converter with Capacitive DAC,” in IEEE International Symposium on Circuits and Systems 2005 (ISCAS 2005), May 2005, pp. 184-187.
  • [8] H. Kim, Y. Min, Y. Kim, and S. Kim, “A Low Power Consumption 10-bit Rail-to-Rail SAR ADC Using a C-2C Capacitor Array,” in IEEE International Conference on Electron Devices and Solid-State Circuits 2008 (EDSSC 2008), Dec. 2008, pp. 1-4.
  • [9] S. Haenzsche, S. Henker, and R. Schuffny, “Modelling of Capacitor Mismatch and Non-Linearity Effects in Charge Redistribution SAR ADCs,” in Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Jun. 2010, pp. 300-305.
  • [10] P. Harpe, C. Zhou, X. Wang, G. Dolmans, and H. de Groot,“ A 30 fJ/Conversion-Step 8b 0-to-10MS/s Asynchronous SAR ADC in 90nm CMOS,” in 2010 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Feb. 2010, pp. 388-389.
  • [11] J. R. Baker, CMOS Circuit Design, Layout and Simulation, 2nd ed. Wiley-IEEE Press, 2004.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-f7729d9e-647c-49eb-b402-883bb4735209
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