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A Graphical Modelling Editor for STARSoC Design Flow Tool Based on Model Driven Engineering Approach

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Języki publikacji
EN
Abstrakty
EN
Background : Due to the increasing complexity of embedded systems, system designers use higher levels of abstraction in order to model and analyse system performances. STARSoC (Synthesis Tool for Adaptive and Reconfigurable System-on-Chip) is a tool for hardware/software co-design and the synthesis of System-on-Chip (SoC) starting from a high level model using the StreamsC textual language. The process behaviour is described in the C syntax language, whereas the architecture is defined with a small set of annotation directives. Therefore, these specifications bring together a large number of details which increase their complexity. However, graphical modelling is better suited for visualizing system architecture. Objectives : In this paper, the authors propose a graphical modelling editor for STARSoC design tool which allows models to be constructed quickly and legibly. Its intent is to assist designers in building their models in terms of the UML Component-like Diagram, and in the automatic translation of the drawn model into StreamsC specification. Methods : To achieve this goal, the Model-Driven Engineering (MDE) approach and well-known frameworks and tools on the Eclipse platform were employed. Conclusion : Our results indicate that the use of the Model-Driven Engineering (MDE) approach reduces the complexity of embedded system design, and it is sufficiently flexible to incorporate new design needs.
Rocznik
Strony
9--26
Opis fizyczny
Bibliogr. 33 poz., rys.
Twórcy
autor
  • Department of Computer Science, Mohamed Seddik Ben Yahia University, Jijel, Algeria
  • LE2I Laboratoire, , University of Bourgogne, Dijon, France
autor
  • MISC Laboratory, Department of Computer Science and its Applications, Faculty of IT, Abdelhamid Mehri University, Constantine, Algeria
Bibliografia
  • [1] M. Gokhale, sc2 Reference Manual, Los Alamos National Laboratory, Los Alamos, NM, USA, 2003.
  • [2] W. Meeus, K.V. Beeck, T. Goedemé, J. Meel, and D. Stroobandt, “An overview of today’s high-level synthesis tools,” Design Automation for Embedded Systems, Vol. 16, No. 3, Aug. 2012, pp. 31–51.
  • [3] J. Cong, B. Liu, S. Neuendorffer, J. Noguera, K.A. Vissers, and Z. Zhang, “High-level synthesis for FPGAs: From prototyping to deployment,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, No. 4, Apr. 2011, pp. 473–491.
  • [4] A. Samahi and E. Bourennane, “Automated integration and communication synthesis of reconfigurable MPSoC platform,” in Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS), University of Edinburgh. Scotland, United Kingdom: IEEE Computer Society, Aug. 2007, pp. 379–385.
  • [5] M. B.Gokhale, J.M. Stone, J. Arnold, and M. Kalinowski, “Stream-oriented FPGA computing in the Streams-C high level language,” in Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines. Napa Valley, CA, USA: IEEE Computer Society, Apr. 2000, pp. 49–56.
  • [6] Unified Modeling Language, Version 2.5, Object Management Group, 2015, OMG Document Number: formal/15-03-01. [Online].http://www.omg.org/spec/UML/2.5/PDF
  • [7] A.R. da Silva, “Model-driven engineering,” Computer Languages, Systems and Structures, Vol. 43, No. C, Oct. 2015, pp. 139–155.
  • [8] J. Joven, O. Font-Bach, D. Castells-Rufas, R. Martínez, L. Terés, and J. Carrabina, “xENoC – an experimental network-on-chip environment for parallel distributed computing on NoC-based MPSoC architectures,” in 16th Euromicro International Conference on Parallel, Distributed and Network-Based Processing. Toulouse, France: IEEE Computer Society, Feb. 2008, pp. 141–148.
  • [9] D. Thomas and P. Moorby, The Verilog Hardware Description Language, 3rd ed. Norwell, MA, USA: Kluwer Academic Publishers, 1996.
  • [10] J. Keinert, M. Streubuhr, T. Schlichter, J. Falk, J. Gladigau, C. Haubelt, J. Teich, and M. Meredith, “SystemCoDesigner – an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications,” ACM Transactions on Design Automation of Electronic Systems, Vol. 14, No. 1, Jan. 2009, pp. 1–23.
  • [11] T. Grotker, System Design with SystemC. Norwell, MA, USA: Kluwer Academic Publishers, 2002.
  • [12] SOPC Builder User Guide, Version 1.0, Altera Corporation, San Jose, CA, USA, Dec. 2010, Document Number: UG-01096. [Online].http://www.altera.com/literature/ug/ug_SOPC_builder.pdf
  • [13] EDK Concepts, Tools, and Techniques: A Hands-On Guide to Effective Embedded System Design, Version 13.2, Xilinx Online Documents, Jul. 2011, OMG Document Number: UG683. [Online].http://www.xilinx.com/support/documentation/sw\_manuals/xilinx13\_2/edk\_ctt.pdf
  • [14] Systems Modeling Language (OMG SysML), Version 1.4, Object Management Group, Sep. 2015, OMG Document Number: formal/2015-06-03. [Online].http://www.omg.org/spec/SysML/1.4/
  • [15] A UML Profile for MARTE: Modeling and Analysis of Real-Time Embedded systems, Version Beta 2, Object Management Group, Jun. 2008, OMG Document Number: ptc/2008-06-09. [Online].http://www.omg.org/omgmarte/Documents/Specifications/08-06-09.pdf
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  • [19] UML Profile for System on a Chip (SoC), Version 1.0.1, Object Management Group, Aug. 2006, OMG Document Number: formal/2006-08-01. [Online].http://www.omg.org/spec/SoCP/1.0.1/PDF
  • [20] T. Kangas, P. Kukkala, H. Orsila, E. Salminen, M. Hännikäinen, T.D. Hämäläinen, J. Riihimäki, and K. Kuusilinna, “UML-based multiprocessor SoC design framework,” ACM Transactions on Embedded Computing Systems, Vol. 5, No. 2, May 2006, pp. 281–320.
  • [21] S. Boukhechem and E. Bourennane, “SystemC transaction-level modeling of an MPSoC platform based on an open source ISS by using interprocess communication,” International Journal of Reconfigurable Computing, Vol. 2008, Sep. 2008, pp. 1–10.
  • [22] J. Frigo, sc2 Hardware Library Reference Manual, Los Alamos National Laboratory, Los Alamos, NM, USA, 2000.
  • [23] L. Cai and D. Gajski, “Transaction level modeling: An overview,” in Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. Newport Beach, CA, USA: ACM, Oct. 2003, pp. 19–24.
  • [24] Eclipse modelling project (EMP). [Online].http://www.eclipse.org/modeling/[Accessed 2016].
  • [25] R.C. Gronback, Eclipse Modeling Project: A Domain-Specific Language (DSL) Toolkit, 1st ed. Addison-Wesley Professional, 2009.
  • [26] Eclipse modelling framework (EMF). [Online].https://eclipse.org/modeling/emf/[Accessed 2016].
  • [27] D. Steinberg, F. Budinsky, M. Paternostro, and E. Merks, EMF: Eclipse Modeling Framework 2.0, 2nd ed. Addison-Wesley Professional, 2009.
  • [28] Graphical editing framework (GEF). [Online].http://www.eclipse.org/gef/[Accessed 2016].
  • [29] Graphical modelling framework (GMF)). [Online].http://www.eclipse.org/modeling/gmp/[Accessed 2016].
  • [30] User Guide, Version 3.1.0, The Eclipse Foundation, 2011. [Online].http://www.eclipse.org/acceleo/support/
  • [31] MOF Model to Text Transformation Language, Version 1.0, Object Management Group, Jun. 2008, OMG Document Number: formal/2008-01-16. [Online].http://www.omg.org/spec/MOFM2T/
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  • [33] OCLinEcore editor. [Online].https://wiki.eclipse.org/MDT/OCLinEcore[Accessed 2016].
Uwagi
PL
Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2018).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-f5cdc06e-81df-4b65-b408-82662acb7075
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