High-voltage SoI Unity-gain Voltage Buffers with Function-enable and Power-down Functionality

• Autorzy: Jankowski M. , Napieralski A.
• Języki publikacji: EN

Abstrakty

EN

This paper discusses possibilities of enable and power-down functionality implementation in HV SoI unity-gain buffers. Modifications of selected HV buffer structures are analyzed. Approaches of power-down, high input and output impedance functionality implementation are introduced and discussed.

Słowa kluczowe

EN

high-voltage integrated circuits; SoI process; high impedance state; enable functionality

PL

wysokonapięciowy układ scalony; proces SoI; stan wysokiej impedancji

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2013
• Tom: Vol. 4, nr 1
• Strony: 26--31
• Opis fizyczny: Bibliogr. 11 poz.

Twórcy

autor

Jankowski M.

• Department of Microelectronics and Computer Science, Lodz University of Technology, Poland

autor

Napieralski A.

• Department of Microelectronics and Computer Science, Lodz University of Technology, Poland

Bibliografia

• [1] M. Jimenez, A. Torralba, R. G. Carvajal, J. Ramirez-Angulo, “A new low-voltage CMOS unity-gain buffer,” Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS 2006, pp. 919-922, 21-24 May 2006.
• [2] H. Barthélemy, E. Kussener, “High speed voltage follower for standard BiCMOS technology,” IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing , vol. 48, no. 7, pp. 727-732, 2001.
• [3] S. Wongfoo, W. Naklo, A. Suadet, V. Kasemsuwan, “A Simple Rail-To-Rail Cmos Voltage Follower,” IEEE Region 10 Conference - TENCON 2006, pp. 1-4, 14-17 Nov. 2006.
• [4] A. Kanjanop, A. Suadet, P. Singhanath, T. Thongleam, S. Kuankid, V. Kasemsuwan, “An Ultra Low Voltage Rail-to-Rail DTMOS Voltage Follower,” 4th International Conference on Modeling, Simulation and Applied Optimization - ICMSAO 2011, pp. 496-500, 2011.
• [5] P. Kadanka, A. Rozsypal, “Rail-to-rail voltage follower without feedback,” Electronics Letters, vol. 36 , Issue 2, pp. 104-105, 02/2000.
• [6] M. Jankowski, A. Napieralski, “Novel Structure of CMOS Voltage-to-Current Converter for High Voltage Applications,” Nanotech Conference & Expo 2012, Santa Clara, CA, USA, June 18-21 2012.
• [7] M. Jankowski, A. Napieralski, “High-Voltage High Input Impedance Unity-Gain Voltage Buffer,” Microelectronics Journal, in press.
• [8] Patent issued by Polish Patent Office “Uklad bufora napieciowego,” (Eng. “Voltage Buffer Circ uit”), inventor: Jankowski Mariusz, applicant/holder: Automatix spółka z o.o., application no. 384096, filed: 19 December 2007, exclusive right kind and number WYN: (11) 212837, granted: 19 June 2012, published: 22 June 2012.
• [9] M. Jankowski, A. Napieralski, “Current-Controlled Switches for HV SoI Processes – Structure, Application and Integration in Functional Blocks,” Nanotech Conference & Expo 2013, Washington, DC, USA, May 12-18 2013.
• [10] Y. Moghe, T. Lehmann, T. Piessens, “Nanosecond Delay Floating High Voltage Level Shifters in a 0.35um HV-CMOS Technology,” IEEE Journal of Solid-State Circuits, Volume 46 (2) , 2011.
• [11] M. Jankowski, A. Napieralski, “Current-mode Processing Possibilities in HV SoI Integrated Systems,” Nanotech Conference & Expo 2013, Washington, DC, USA, May 12-18 2013.