Design a High-Performance Memory Controller for a Multimedia SOC

• Autorzy: Chu S.-L. , Lo M.-J.

Warianty tytułu

PL

Projekt kontrolera pamięci o dużej wydajności w przeznaczeniu do multimedialnych elementów SOC

• Języki publikacji: EN

Abstrakty

EN

Continuously growing functionalities of modern consuming electronics make the major multimedia SOC (system-on-a-chip) chip more complex. Moreover, the integrated multimedia processors and the required memory bandwidth are increasing. Therein how to improve the performance of the memory controller will become a major challenge of designing a modern multimedia SOC. According to our previous study of multimedia SOC, to achieving the bandwidth requirements are not only by improving memory throughput but also by dynamically adjusting the bandwidth usage of multimedia processors. Therefore we develop novel memory subsystem, called Smart Memory Controller (SMC), which integrates a novel scheduling/arbitration mechanism, a unified access buffer, multi-level memory access classification/scheduling, and several corresponding hardware modules, to provide a sufficient memory bandwidth for the multimedia processors with high bandwidth requirements. The proposed SMC architecture has been implemented by SystemC/Bluespec/Verilog HDL. The experimental results from whole SMC system illustrates that SMC will arrange enough bandwidth for the channels that have bursting transferring requirement. The fabrication results of SMC are also provided.

PL

W artykule zaproponowano nowy system pamięci nazwany SMC (smart memory controller) przeznaczony do multimedialnych elementów typu SOC (system on a chip). System integruje mechanizm planowania i arbitrażu (scheduling/arbitration), bufor dostępu, wielopoziomowy dostęp do pamięci i wiele innych modułów.

Słowa kluczowe

EN

memory access scheduling; multimedia system-on-a-chip; interconnection network; system C

PL

SOC; kontroler pamięci

• Wydawca: Wydawnictwo SIGMA-NOT
• Czasopismo: Przegląd Elektrotechniczny
• Rocznik: 2012
• Tom: R. 88, nr 7b
• Strony: 353--356
• Opis fizyczny: Bibliogr. 5 poz., schem., wykr.

Twórcy

autor

Chu S.-L.

• Department of Information and Computer Engineering, Chung Yuan Christian University, 200, Chung Pei Rd., Chung Li, 32023 Taiwan

autor

Lo M.-J.

• Department of Information and Computer Engineering, Chung Yuan Christian University, 200, Chung Pei Rd., Chung Li, 32023 Taiwan

Bibliografia

• [1] Kornaros G., Papaefstathiou I., Nikologiannis A., and Zervos N, A Fully-Programmable Memory Management System Optimization Queue Handling at Multi Gigabit Rate. In: 40th Conference on Design Automation, 2003.
• [2] Nieh J., and Lam M. S., The Design, Implementation and Evaluation of SMART: A Scheduler for Multimedia Applications. In: ACM symposium on Operating Systems Principles, 1997.
• [3] Vlachos K., N., Nikolaou T. Orphanoudakis, S. Perissakis, Pnevmatikatos D., Kornaros G., Sanchez J. A., and Konstantoulakis G., Processing and Scheduling Components in an Innovative Network Processor Architecture. In: 16th International Conference on VLSI Design, 2003.
• [4] Sonics Ltd., MemMax Memory Controller. http://www.sonicsinc.com/.
• [5] Chu S. L., Lo M. J., and Yang H. W., MediaMem: A Dynamically Adjustable Memory Subsystem for Highbandwidth Required Multimedia SoC Systems. In: 13th Asia-Pacific Computer Systems Architecture Conference, 2008.