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A comprehensive performance investigation on ingenious ECC co-processor architecture for Different Multipliers

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Warianty tytułu
PL
Badania właściwości koprocesorów ECC w zastosowaniu do mnożników
Języki publikacji
EN
Abstrakty
EN
This paper proposes an Elliptic Curve Cryptography (ECC) co-processor over GF(2256), based on the Montgomery scalar multiplication algorithm and provides a comprehensive evaluation of the architecture when different multipliers are involved in the scalar multiplication. The multipliers, namely array multiplier, modified Booth multiplier and hybrid encoded low power (HELP) multiplier are considered for the study. The proposed architecture is designed using Spartan3E family device XC3S1600E and synthesized using Modelsim 5.7.
PL
W artykule zaproponowano algorytm mnożenia bazujący na mnożeniu skalarnym typu Montgomery. Rozważano różne architektury – matrycowe, mnożnik typu Booth i hybrydowy zakodowany mnożnik małej mocy HELP.
Rocznik
Strony
157--161
Opis fizyczny
Bibliogr. 19 poz., schem., tab.
Twórcy
autor
  • Department of Computer Science and Engineering, Surya Group of Institutions, Villupuram, TamilNadu, India
autor
  • Department of ECE, Adhiparasakthi Engineering College, Melmaruvathur, TamilNadu, India
Bibliografia
  • [1]. N. Koblitz, “Elliptic Curve Cryptosystems”, Mathematical on Computer, vol.48, no.177, pp.203-209, 1987.
  • [2]. V.S. Miller, “Use of Elliptic Curves in Cryptography”, Proceeding of the International Conference on Advances in Cryptology (CRYPTO ’85), Springer-Verlag, LNCS 218, pp.417–426, 1986.
  • [3]. R. Rivest, A. Shamir and L. Adleman, “A Method for Obtaining Digital Signatures and Public Key Cryptosystems”, Communication on ACM, vol.21, no.2, pp.120-126, 1978.
  • [4]. A. Menezes, “Elliptic Curve Public Key Cryptosystems”, 1st Edition, Kluwer Academic Publishers, ISBN-13: 978-0792393689, 1993.
  • [5]. D. Hankerson, A. Menezes, and S. Vanstone, “Guide to Elliptic Curve Cryptography”, 1st Edition, Springer, 2004.
  • [6]. Yinan Kong, “Optimizing the Improved Barrett Modular Multipliers for Public-Key Cryptography”, Proceeding of IEEE Conference on Computational Intelligence and Software Engineering (CISE’10), pp.1-4, 2010.
  • [7]. Marisa W. Paryasto, Budi Rahardjo, Fajar Yuliawan, Intan Muchtadi-Alamsyah, Kuspriyanto, “ Composite Field Multiplier based on Look-Up Table for Elliptic Curve Cryptography Implementation”, Proceeding of the IEEE International Conference on Electrical Engineering and Informatics, Bandung, Indonesia , pp.1-4, July 2011,
  • [8]. Mark Hamilton, William P. Marnane, Arnaud Tisserand, “A Comparison on FPGA of Modular Multipliers Suitable for Elliptic Curve Cryptography over GF(p) for Specific p Values”, Proceeding of the IEEE 21st International Conference on Field Programmable Logic and Applications, pp.273-276, 2011.
  • [9]. Justin Hensley, Anselmo Lastra and Montek Singh, “ An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile Devices”, Proceedings of the IEEE International Conference on Computer Design, pp.18-25, 2004.
  • [10]. Sandeep Kumar, Thomas Wollinger, and Christof Paar, “Optimum Digit Serial GF(2m) Multipliers for Curve-Based Cryptography”, IEEE Transactions on Computers, vol.55, no.10, pp.1306-1311, October 2006.
  • [11]. Al-Somani T.F. and Houssain H., “Implementation of GF(2m) Elliptic Curve Crypto- processor on a Nano FPGA”, Proceeding of the IEEE International Conference on Internet Technology and Secured Transactions (ICITST), Abu Dhabi, United Arab Emirates, pp. 7-12, 2011.
  • [12]. IEEE 1363, Standard Specifications for Public key Cryptography, 2000.
  • [13]. S.Saravanan and M.Madheswaran, “Design and Analysis of a Spurious Switching Suppression Technique Equipped Low Power Multiplier with Hybrid Encoding Scheme”, International Journal of Computer Science and Information Security, vol.6, no.3, pp.73-78, 2009.
  • [14]. S.Saravanan and M.Madheswaran, “Design of Hybrid Encoded Booth Multiplier with Reduced Switching Activity Technique and Low Power 0.13μm Adder for DSP Block in Wireless Sensor Node”, Proceeding on IEEE Conference on Wireless Communication and Sensor Computing, pp.1-6, 2010.
  • [15]. Yaxun Gong and Shuguo Li, “High-Throughput FPGA Implementation of 256-bit Montgomery Modular Multiplier”, Proceeding of the IEEE International Conference on Education Technology and Computer Science (ETCS), vol.3, p. 173-176, 2010.
  • [16]. Zhang Jiahong, Xiong Tinggang, and Fang Xiangyan, “A Fast Hardware Implementation of Elliptic Curve Cryptography”, Proceeding of the IEEE International Conference on Information Science and Engineering (ICISE), pp. 1519–1522, 2009.
  • [17]. McIvor, McLoone, and McCanny, “ Hardware Elliptic Curve Cryptographic Processor Over GF(p)”, IEEE Transaction on Circuits and Systems I: Regular Papers, vol.53, no.9, pp.1946–1957, 2006.
  • [18]. K. Tanimura, R. Nara, and S. Kohara, “ Scalable unified dualradix architecture for Montgomery multiplication in GF(P) and GF(2n)”, Proceeding of the IEEE International Conference on Design Automation Conference, pp. 697–702, 2008.
  • [19]. K. Ananyi, H. Alrimeih and D. Rakhmatov, “ Flexible Hardware Processor for Elliptic Curve Cryptography Over NIST Prime Fields”, IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol.17, no.8, pp. 1099 - 1112, 2009.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-ee4a71f8-aad6-4ad4-97d4-b82b7c2d19d1
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