The True Random Number Generator design using a high-noise oscillator

• Autorzy: Butryn Igor , Derlecki Mariusz , Łuczyk Arkadiusz , Jasiński Jakub , Wielgus Andrzej , Siwiec Krzysztof

Identyfikatory

DOI

10.24425/ijet.2025.155477

• Języki publikacji: EN

Abstrakty

EN

The growing importance of creating appropriate safeguards in electronic systems forces design of integrated circuits dedicated for cryptographic purposes. The paper focuses on True Random Number Generator (TRNG) circuits design allowing generation of random bit stream. Presented TRNG architecture uses low frequency high-noise oscillator for sampling high frequency clock signal. The article also describes a method for obtaining a high noise level in the oscillator. Achieved bit rate of designed TRNG equals 1 Mb/s. The circuit dissipates 144 μW. The design of the TRNG, simulation and measurement results of the manufactured IC chips have been described in the paper also. TRNG circuit has been implemented in 180 nm CMOS technology.

Słowa kluczowe

EN

TRNG; Cryptography; Encryption; Random Numbers; Jitter

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2025
• Tom: Vol. 71, No. 4
• Strony: 24
• Opis fizyczny: Bibliogr., 12 poz., fot., rys., tab.

Twórcy

autor

Butryn Igor

• Warsaw University of Technology

autor

Derlecki Mariusz

• Techinsights Europe Sp. z o.o. Poland

autor

Łuczyk Arkadiusz

• Warsaw University of Technology

autor

Jasiński Jakub

• Warsaw University of Technology

autor

Wielgus Andrzej

• Warsaw University of Technology

autor

Siwiec Krzysztof

• Warsaw University of Technology

Bibliografia

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• [3] M. Derlecki, K. Siwiec, P. Narczyk and W. A. Pleskacz, "Design of a True Random Number Generator Based on Low Power Oscillator with Increased Jitter," 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Cluj-Napoca, Romania, 2019, pp. 1-4, https://doi.org/10.1109/DDECS.2019.8724643
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• [10] A. Emira, E. Sanchez-Sinencio and M. Schneider, "Design tradeoffs of CMOS current mirrors using one-equation for all-region model," 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), Phoenix-Scottsdale, AZ, USA, 2002, pp. V-V, https://doi.org/10.1109/ISCAS.2002.1010636
• [11] L. N. Alves and R. L. Aguiar, "Noise performance of classical current mirrors," in Proc. 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS), vol. 1, Dubrovnik, Croatia, Sept. 2002, pp. 277-280, https://doi.org/10.1109/ICECS.2002.1045387
• [12] A. L. Rukhin, J. Soto, J. R. Nechvatal, M. E. Smid, E. B. Barker, S. D. Leigh, M. Levenson, M. Vangel, D. L. Banks, A. Heckert, J. F. Dray Jr. and S. C. Vo, "A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications," NIST Special Publication 800‑22, April 2010.

Uwagi

This work was supported in part by the Polish National Center for Research and Development under project No. CYBERSECIDENT/369203/I/NCBR/2017.