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On In-System Programming of Non-volatile Memories

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Języki publikacji
EN
Abstrakty
EN
With the continuous growth of capacity of non-volatile memories (NVM) in-system programming (ISP) has become the most time-consuming step in post-assembly phase of board manufacturing. This paper presents a method to assess ISP solutions for on-chip and on-board NVMs. The major contribution of the approach is the formal basis for comparison of state-of-the-art ISP solutions. The effective comparison pin-points the time losses, that can be eliminated by the use of multiple page buffers. The technique has proven to achieve exceptionally short programming time, which is close to the operational speed limit of modern NVMs. The method is based on the ubiquitous JTAG access bus which makes it applicable for the most board manufacturing strategies despite a slow nature of JTAG bus.
Twórcy
autor
  • Department of Computer Engineering, Tallinn University of Technology, Tallinn, Estonia
autor
  • Testonica Lab OU, Tallinn, Estonia
autor
  • Testonica Lab OU, Tallinn, Estonia
autor
  • Testonica Lab OU, Tallinn, Estonia
Bibliografia
  • [1] IEEE Standard Test Access Port and Boundary-Scan Architecture , IEEE Std. 1149.1-2001, 2001.
  • [2] IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture , IEEE Std. 1149.7-2009, 2010.
  • [3] P. Maxwell, I. Hartanto, and L. Bentz, “Comparing functional and structural tests,” in Proc. of International Test Conference , Atlantic City, NJ , USA, 2000, pp. 403–407.
  • [4] J. Webster, B. Fenton, D. Stringer, and B. Bennetts, “On the synergy of boundary scan and emulation board test: a case study,” in Proc. of Board Test Workshop , Charlotte, USA, 2003, p. 10.
  • [5] (2010) High speed programming of non-volatile memories using the xjtag development system. White Paper. XJTAG. [Online]. Available: http://www.xjtag.com/
  • [6] A. Tsertov, R. Ubar, A. Jutman, and S. Devadze, “Automatic soc level test path synthesis based on partial functional models,” in Proc. of 20th Asian Test Symposium (ATS) , New Delhi, India, 2011, pp. 532 – 538.
  • [7] (2009) Combining boundary scan and jtag emulation for advanced structural test and diagnostics. White Paper. T. Wenzel and H. Ehrenberg. [Online]. Available: http://tmworld.resourcecenteronline.com
  • [8] S. Devadze, A. Jutman, A. Tsertov, M. Instenberg, and R. Ubar, “Microprocessor-based system test using debug interface,” in Proc. of 26th IEEE NORCHIP Conference , Tallinn, Estonia, Nov. 2008, pp. 98–101.
  • [9] T. Wenzel and H. Ehrenberg. (2009) Combining boundary scan and JTAG emulation for advanced structural test and diagnostics: White paper. Goepel Electronic GmbH. Jena, Germany. [Online]. Available: http://tmworld.resourcecenteronline.com
  • [10] XC236xE Data Sheet , V1.2 2012-06, Infineon Technologies AG, 2012.
  • [11] (2009) Getting started. creating applications with uvision4. Manual. Keil, Tools by ARM, and ARM Ltd. [Online]. Available: http://www.keil.com/product/brochures/uv4.pdf
  • [12] (2012) Jtag/boundary scan is probably the most ingenious test process. Web Article. Goepel Electronic Ltd. [Online]. Available: http://www.goepel.com/en/jtag-boundary-scan/boundary-scan-instruments.html
  • [13] M29EW Datasheet , 208045-10, Numonyx Axcell, 2010.
  • [14] ARM Architecture Reference Manual - ARMv7-A and ARMv7-R edition , ARM DDI 0406C, ARM Limited, 2011.
  • [15] ARM Debug Interface v5 Architecture Specification , ARM IHI 0031A, ARM Limited, 2006.
  • [16] MT29F2 Datasheet , m79m 2gb nand, Micron, 2010.
  • [17] Zynq-7000 EPP Technical Reference Manual , UG585 (v1.1), Xilinx, 2012.
  • [18] N25Q128 1.8V Datasheet , Rev 1.0, Numonyx Axcell, 2010.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-ec96eadf-df45-4c6d-af56-2578a962a376
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