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A simple and accurate CMOS Sample-and-Hold Circuit using Dual Output-OTA

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PL
Prosty i dokładny układ Sample-and-Hold wykorzystujący transkondukltancyjny wzmacniacz DO-OTA
Języki publikacji
EN
Abstrakty
EN
A new CMOS sample-and-hold (S/H) circuit using dual output-operational transconductance amplifier (DO-OTA), one resistor and one capacitor is presented. It is unlike conventional S/H circuit. The proposed circuit has not use a switched-capacitor, switched-current or MOS switches for on-off switch but it uses an on-off DO-OTA by bias current that replace them. The proposed S/H circuit is high speed on-off status of switch and without buffer circuit can be obtained. However, it is a very simple circuit, high accuracy, low-power consumption and suitable for signal processing applications by using on the first part of analog to digital converter. The simulation results are used to confirm the workability of the proposed circuit.
PL
W pracy zaprezentowano nową koncepcję układu sample and Hold bazującą na transkonduktancyjnym wzmacniaczu DO-OYA. Proponowany układ nie wykorzystuje przełączanego kondensatora I zamast tego wykorzystuje przełączany prąd układu DO-OTA.
Rocznik
Strony
163--166
Opis fizyczny
Bibliogr. 27 poz., rys., tab.
Twórcy
  • Department of Electronics and Telecommunications Engineering, Faculty of Industrial Education and Technology, Rajamangala University of Technology Srivijaya Songkhla, Thailand
Bibliografia
  • [1] Rudy V.D.P., CMOS Integrated analog-to-digital and digital-toanalog converters, Netherlands, Kluwer Academic Publishers, (2003)
  • [2] Paul G.A.J., Integrated converters D to A and A to D architectures, analysis and simulation, New York, Oxford University Press, (2004)
  • [3] Behzad R., Design of sample-and-hold amplifiers for highspeed low-voltage A/D converters, in Proceedings of IEEE Custom Integrated Circuits Conference, USA, (1997), 59-66
  • [4] Prakruthi T.G., Siva Y., Design and implementation of sample and hold circuit in 180nm CMOS technology, in Proceedings of IEEE International Conference on Advances in Computing, Communications and Informatics, India, (2015), 1148-1151
  • [5] Kumar K.S., Krishna K.L., Raghavendra K.S., Harish K., A High Speed Flash Analog to Digital Converter, in Proceedings of IEEE International Conference on IoT in Social, Mobile, Analytics and Cloud, India, (2018), 283-288
  • [6] Andrea B., Andrea P., Carlo M., A 10-b 185-MS/s track-andhold in 0.35-µm CMOS, IEEE Journal of Solid-State Circuits, 36 (2001), 195-203
  • [7] Tchamov N., Velichkov M., Keranen A., Stoyanov V., Differentially pre-compensated GHz range low-voltage trackand- hold, IEE Electronics Letters, 39 (2003), 180
  • [8] Rijns J. J. F., Wallinga H., Stray-insensitive switched-capacitor sample-delay-hold buffers for video frequency applications, Electronics Letters, 27 (1991), 639-640
  • [9] Seng-Pan U., Rui P.M., Jose E.F., Improved switchedcapacitor interpolators with reduced sample-and-hold effects, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 47 (2000), 665-684
  • [10] Francesco C., Andrea S., Alessandro T., Switched capacitor sample-and-hold circuit with input signal range beyond supply voltage, in Proceedings of IEEE 26th NORCHIP conference, Estonia, (2008), 75-78
  • [11] Mohammadreza A., A high-speed comparator-based switchedcapacitor sample and hold circuit, in Proceedings of Iranian Conference on Electrical Engineering, Iran, (2017), 249-252
  • [12] Walter G., Jiandong D., Josef G., Switched-current memory circuits for high-precision applications, IEEE Journal of Solid- State Circuits, 29 (1994), 1108–1116
  • [13] Jorge M.M., Victor F.D., Harmonic distortion in switchedcurrent audio memory cells, IEEE Transactions on Circuits and Systems II, 46 (1999), 326–334
  • [14] Ganesh K.B., Phillip E.A., Switched current circuits in digital CMOS technology with low charge-injection errors, IEEE Journal of Solid-State Circuits, 37 (2002), 1271- 1281
  • [15] Apisak W., John B.H., Chris T., A low-power high-frequency class-AB two-step sampling switched-current techniques, IEEE Transactions on Circuits and Systems II, 50 (2003), 649-653
  • [16] Guo-Ming S., Wen-Sheng L., Jiung-Shian L., A 9-bit 123-MS/s switched-current pipelined ADC with OP feedback and offset current cancellation, in Proceedings of IEEE 56th International Midwest Symposium on Circuits and Systems, USA, (2013), 673-676
  • [17] Shan-Hao S., Jonathan H., Chih-Ping Y., A 10-bit 200-MS/s switched-current pipelined ADC for analog front end of XDSL, in Proceedings of IEEE 7th International Symposium on Next Generation Electronics, Taipei, (2018), 1-3
  • [18] Reimann T., Kreummenacher F., Declercq M.J., An 8-b, 40 Ms/s switched-current-mode track-and-hold circuit on a BiCMOS sea-of-gates array, IEEE Journal of Solid-State Circuits, SC-31 (1996), 304–311
  • [19] Seon J. K., A 10-b 120-MS/s CMOS track-and-hold amplifier, Analog Integrated Circuits and Signal Processing, 44 (2005), 55–60
  • [20] Ronak T., Low power and high speed sample-and-hold circuit, in Proceedings of IEEE 49th International Midwest Symposium on Circuits and Systems, Puerto Rico, (2006), 453-456
  • [21] Seon J. K., Nam K. H., Kang S. H., Bae K. S., Kim J. B., A simple and accurate track-and-hold circuit using operational transconductance amplifier, in Proceedings of IEEE 14th International Conference on Mixed Design of Integrated Circuits and Systems, Poland, (2007), 215-218
  • [22] Liu Z., Cheng J., Zhang H., Chen G., The design and optimization of gain-boosted OTA for high speed and high accuracy sample and hold amplifier, in Proceedings of IEEE 7th International Conference on ASIC, China, (2007), 461-464
  • [23] Francesco C., Andrea S., Alessandro T., A low-power sampleand- hold circuit based on a switched-opamp technique, in Proceedings of IEEE International Conference on Signals and Electronic Systems, Poland, (2008), 105-108
  • [24] Mahmoud Z., Hossein A., Behjat F., Design of a two-capacitor sample & hold circuit using a two-stage OTA with hybrid cascode compensation, in Proceedings of IEEE European Conference on Circuit Theory and Design, Turkey, (2009), 493- 498
  • [25] Montree K., Thanat N., Fabian K., Low-power sample and hold circuits using current conveyor analogue switches, IET Circuits, Devices & Systems, 12 (2018), 397-402
  • [26] Montree K., Boonying K., Kobchai D., Electronically tunable high-input impedance voltage-mode universal biquadratic filter based on simple CMOS OTAs, International Journal of Electronics and Communications, 64 (2010), 934-939
  • [27] http://www.mosis.com/pages/Technical/Testdata/tsmc-018- prm
Uwagi
Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2020).
Typ dokumentu
Bibliografia
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bwmeta1.element.baztech-ec5897a3-b96c-4749-883b-fd5f639c5b0c
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