Instruction driven CPU in the FPGA structure

• Autorzy: Gracki K. , Pawłowski M. , Skorupski A. , Szymański Z.
• Języki publikacji: EN

Abstrakty

EN

The paper presents the design of processors embedded in an FPGA structure. The type of processor is determined by the preset instruction list. Each instruction is implemented as one functional block attached to a common bus. The processor contains two additional blocks: one contains a common register block and second is responsible for the fetch of the instruction from the program memory. To design the processor, one can choose the instruction set from the library of instructions components. The library is a set of VHDL descriptions of all possible instructions.

Słowa kluczowe

EN

processor; FPGA systems; VHDL language

• Wydawca: Wydawnictwo PAK
• Czasopismo: Measurement Automation Monitoring
• Rocznik: 2016
• Tom: Vol. 62, No. 5
• Strony: 169--171
• Opis fizyczny: Bibliogr. 9 poz., schem., tab.

Twórcy

autor

Gracki K.

• Institute of Computer Science Warsaw University of Technology, 15/19 Nowowiejska, 00-665 Warszawa

autor

Pawłowski M.

• Institute of Computer Science Warsaw University of Technology, 15/19 Nowowiejska, 00-665 Warszawa

autor

Skorupski A.

• Institute of Computer Science Warsaw University of Technology, 15/19 Nowowiejska, 00-665 Warszawa

autor

Szymański Z.

• Institute of Computer Science Warsaw University of Technology, 15/19 Nowowiejska, 00-665 Warszawa

Bibliografia

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• [8] Reaz M. B. I., Jalil J., and Rahman L. F.: Single Core Hardware Modeling of 32-bit MIPS RISC Processor with A Single Clock. Research Journal of Applied Sciences, Engineering and Technology 4(7): 825-832, 2012.
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