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Tytuł artykułu

Design and analyses of a low power linear voltage regulator in 0.18μm CMOS process

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Warianty tytułu
PL
Projekt i analiza regulatora napięcia o małym poborze mocy wykonanego w technologii CMOS 0.18 μm
Języki publikacji
EN
Abstrakty
EN
Linear voltage regulator is inevitable in most electronic systems and demands low power and low area. A low dropout (LDO) linear voltage regulator is proposed in this paper by utilizing Current Feedback Amplifier (CFA) technology. The design achieves low power and low area by reducing the internal compensation capacitor and resistors. The simulated result shows that the design consumes only 567.1370pW which is 35% less than the reference circuit. The design also achieves low area and higher gain.
PL
W artykule omówiono liniowy regulator napięcia wykorzystujący koncepcję LDO (low dropout ). Układ wykorzystuje wzmacniacz z prądowym sprzężeniem zwrotnym CFA I technologię CMOS. Zrealizowano układ pobierający o 35% mniej energii niż układy znane z literatury.
Rocznik
Strony
201--203
Opis fizyczny
Bibliogr. 19 poz., schem., tab., wykr.
Twórcy
autor
  • Department of Electrical, Electronic and Systems Engineering,Universiti Kebangsaan Malaysia, 43600 UKM, Bangi, Selangor, Malaysia
autor
  • Department of Electrical, Electronic and Systems Engineering,Universiti Kebangsaan Malaysia, 43600 UKM, Bangi, Selangor, Malaysia
  • Department of Electrical, Electronic and Systems Engineering,Universiti Kebangsaan Malaysia, 43600 UKM, Bangi, Selangor, Malaysia
autor
  • Department of Electrical, Electronic and Systems Engineering,Universiti Kebangsaan Malaysia, 43600 UKM, Bangi, Selangor, Malaysia
autor
  • Department of Electrical, Electronic and Systems Engineering,Universiti Kebangsaan Malaysia, 43600 UKM, Bangi, Selangor, Malaysia
Bibliografia
  • [1] Mohd-Yasin F., Khaw M. K., Reaz M. B. I., Radio frequency identification: Evolution of transponder circuit design, Microwave Journal, 49(2006), 56-70.
  • [2] Uddin J., Reaz M. B. I., Hasan M. A., Nordin A. N., Ibrahimy M. I., Ali M. A. M., UHF RFID antenna architectures and applications, Scientific Research and Essays, 5(2010), 1033- 1051.
  • [3] Rahman L. F., Reaz M. B. I., Ali M. A. Mohd., Kamada M., Design of an EEPROM in RFID tag: Employing mapped EPC and IPv6 address, in Proc. of the IEEE Asia-Pacific Conference on Circuits and Systems, (APCCAS 2010), 2010, 168-171.
  • [4] Mohd-Yasin F., Khaw M. K., Reaz M. B. I., Techniques of RFID systems: Architectures and applications, Microwave Journal, 49(2006), 62-74.
  • [5] Amin M. S., Reaz M. B. I., Rahman L. F., Jalil J., Digital Modulator and Demodulator IC for RFID Tag Employing DSSS and Barker Code, Journal of Applied Research and Technology, vol. 10(2012), No. 6, 819-825,.
  • [6] Amin M. S., Reaz M. B. I., Jalil J., Design of a novel adder‐less Barker matched filter for RFID, International Journal of Circuit Theory and Applications, DOI: 10.1002/cta.1895, 2013.
  • [7] Ho Q. T., Vo T. N., Nguyen H. D., Bui N. C., A current sensing circuit using current-voltage conversion for PMOS-based LDO regulators, in Proc. of the IEEE Symposium on Computer Applications and Industrial Electronics (ISCAIE), 2012, 1 – 4.
  • [8] Teh Y. K., Mohd-Yasin F., Choong F., Reaz M. I., Kordesch A. V., Design and analysis of UHF micropower CMOS DTMOST rectifiers, IEEE Transactions on Circuits and Systems II: Express Briefs, 56(2009), 122-126.
  • [9] Khaw M. K., Mohd-Yasin F., Reaz M. I., Recent advances in the integrated circuit design of RFID transponder, in Proc. Of the IEEE International Conference on Semiconductor Electronics (ICSE 2004), 2004, 326-330.
  • [10] Romli N. B., Mamun M., Bhuiyan M. A. S., Husain H., Design of a Low Power Dissipation and Low Input Voltage Range Level Shifter in Cedec 0.18-μm Cmos Process, World Applied Sciences Journal, 19(2012), 1140-1148.
  • [11] Rincon-Mora, G.A. and P.E. Allen, A low-voltage, low quiescent current, low dropout regulator, IEEE Journal of Solid-State Circuits, 33(1998), No. 1, 36-44.
  • [12] Rincon-Mora G. A., Allen P. E., Optimized frequency-shaping circuit topologiesfor LDOs, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 45(1998), No. 6, 703-708.
  • [13] Heisley D., Wank B., DMOS delivers dramatic performance gains to LDO regulators. EDN, 45(2000), No. 13, 141-150.
  • [14] Al-Shyoukh M., Hoi L., Perez R., A transient-enhanced lowquiescent current low-dropout regulator with buffer impedance attenuation, IEEE Journal of Solid-State Circuits, 42(2007), No. 8, 1732-1742.
  • [15] Aziz F. I. B. A., Mamun M., Bhuiyan M. A. S., Bakar A. A. A., A Low Drop-Out Voltage Regulator in 0.18 μm CMOS Technology, Modern Applied Science, 7(2013), No. 4, 70-76.
  • [16] Wonseok O., Bakkaloglu B., A CMOS low-dropout regulator with current-mode feedback buffer amplifier, IEEE Transactions on Circuits and Systems II: Express Briefs, 54(2007), No. 10, 922-926.
  • [17] Saberkari A., Alarcón E., Shokouhi S. B., Fast transient current-steering CMOS LDO regulator based on current feedback amplifier, Integration, The VLSI Journal, 46(2013), No.2, 165-171.
  • [18] Jorge E, João P., Júlio P., Marcelino S., Ultra low power capless LDO with dynamic biasing of derivative feedback, Microelectronics Journal, 44(2013), No.2, 94-102.
  • [19] Wang C.-C., Kou R.-C., Tsai T.-H., A high precision low dropout regulator with nested feedback loops, Microelectronics Journal, 42(2011), No 7, 966-971.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-e79a85ec-d245-4e6d-85f2-4596bdd339d1
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