Jitter generation model based on timing modulation and cross point calibration for jitter decomposition

• Autorzy: Ren Nan , Fu Zaiming , Lei Shengcu , Liu Hanglin , Tian Shulin

Identyfikatory

DOI

10.24425/mms.2021.135993

• Języki publikacji: EN

Abstrakty

EN

High-speed serial standards are rapidly developing, and with a requirement for effective compliance and characterization measurement methods. Jitter decomposition consists in troubleshooting steps based on jitter components from decomposition results. In order to verify algorithms with different deterministic jitter (DJ) in actual circuits, jitter generation model by cross-point calibration and timing modulation for jitter decomposition is presented in this paper. The generated jitter is pre-processed by cross-point calibration which improves the accuracy of jitter generation. Precisely controllable DJ and random jitter (RJ) are generated by timing modulation such as data-dependent jitter (DDJ), duty cycle distortion (DCD), bounded uncorrelated jitter (BUJ), and period jitter (PJ). The benefit of the cross-point calibration was verified by comparing generation of controllable jitter with and without cross-point calibration. The accuracy and advantage of the proposed method were demonstrated by comparing with the method of jitter generation by analog modulation. Then, the validity of the proposed method was demonstrated by hardware experiments where the jitter frequency had an accuracy of ±20 ppm, the jitter amplitude ranged from 10 ps to 8.33 ns, a step of 2 ps or 10 ps, and jitter amplitude was independent of jitter frequency and data rate.

Słowa kluczowe

EN

jitter decomposition; jitter generation; cross-point calibration; timing modulation; deterministic jitter; random jitter

• Wydawca: Komitet Metrologii i Aparatury Naukowej PAN
• Czasopismo: Metrology and Measurement Systems
• Rocznik: 2021
• Tom: Vol. 28, nr 1
• Strony: 123--143
• Opis fizyczny: Bibliogr. 41 poz., rys., tab., wykr., wzory

Twórcy

autor

Ren Nan

• University of Electronic Science and Technology of China, School of Automation Engineering, Chengdu 611731, China

autor

Fu Zaiming

• University of Electronic Science and Technology of China, School of Automation Engineering, Chengdu 611731, China

autor

Lei Shengcu

• University of Electronic Science and Technology of China, School of Automation Engineering, Chengdu 611731, China

autor

Liu Hanglin

• University of Electronic Science and Technology of China, School of Automation Engineering, Chengdu 611731, China

autor

Tian Shulin

• University of Electronic Science and Technology of China, School of Automation Engineering, Chengdu 611731, China

Bibliografia

• [1] Sotiriadis, P. P. (2010). Theory of flying-adder frequency synthesizers - Part I: modeling, signals’ periods and output average frequency. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(5), 1935-1948. https://doi.org/10.1109/TCSI.2009.2039834
• [2] Stephens, R. (2004). Jitter analysis: The dual-Dirac model, RJ/DJ, and Q-scale. [White Paper, v.1.0a]. https://www.keysight.com/upload/cmc_upload/All/dualdirac1.pdf
• [3] Chada, A., Mutnury, B., Dikhaminjia, N., Tsiklauri, M., Fan, J., & Drewniak, J. L. (2018). Improved Transmitter Jitter Modeling for Accurate Bit Error Rate (BER) Eye Contours Using Transient Simulation of Short Bit Patterns. IEEE Transactions on Electromagnetic Compatibility, 60(2), 1520-1528. https://doi.org/10.1109/TEMC.2017.2776080
• [4] Tektronix. (2005). Jitter Generation Techniques for Serializer-Deserializer Compliance Testing. [Application Note]. https://m.eet.com/media-/1109453/tek_18568.pdf
• [5] Li, M. P. (2007). Jitter, noise, and signal integrity at high-speed. Pearson Education.
• [6] Da Dalt, N., & Sheikholeslami, A. (2018). Understanding Jitter and Phase Noise: A Circuits and Systems Perspective. Cambridge University Press.
• [7] Duan, Y., Wu, H., Shimanouchi, M., Li, M. P., & Chen, D. (2018). A Low-Cost Comparator-Based Method for Accurate Decomposition of Deterministic Jitter in High-Speed Links. IEEE Transactions on Electromagnetic Compatibility, 61(2), 521-531. https://doi.org/10.1109/TEMC.2018.2821680
• [8] Mistry, D., Joshi, S., & Agrawal, N. (2015). A novel jitter separation method based on Gaussian mixture model. Proceedings of 2015 International Conference on Pervasive Computing (ICPC). India. https://doi.org/10.1109/PERVASIVE.2015.7087091
• [9] Dou, Q., & Abraham, J. A. (2006, March). Jitter decomposition by time lag correlation. 7th International Symposium on Quality Electronic Design (ISQED’06), USA. https://doi.org/10.1109/ISQED.2006.78
• [10] Ku, C. K., Goay, C. H., Ahmad, N. S., & Goh, P. (2019). Jitter Decomposition of High-Speed Data Signals from Jitter Histograms with a Pole-Residue Representation Using Multilayer Perceptron Neural Networks. IEEE Transactions on Electromagnetic Compatibility, 62(2), 2227-2237. https://doi.org/10.1109/TEMC.2019.2936000
• [11] Soliman G. (2019). Improved Jitter Distribution Tail-Fitting Algorithm for Decomposition of Random and Deterministic Jitter. IEEE Transactions on Electromagnetic Compatibility, 62(2), 1852-1857. https://doi.org/10.1109/TEMC.2019.2947222
• [12] Nan, F., Wang, Y., Li, F., Yang, W., & Ma, X. (2009). A better method than tail-fitting algorithm for jitter separation based on Gaussian mixture model. Journal of Electronic Testing, 25(3), 337. https://doi.org/10.1007/s10836-009-5112-8
• [13] Pang, H., Zhu, J., & Huang, W. (2009). Jitter decomposition by fast Fourier transform and time lag correlation. In 2009 International Conference on Communications, Circuits and Systems, USA, 365-368. https://doi.org/10.1109/ICCCAS.2009.5250491
• [14] Joseph, F., Hilliges, K. D., & Owen, C. L. (2007). U.S. Patent No. 7,184,469. Washington, DC: U.S. Patent and Trademark Office.
• [15] Calvin, J. C., & Richmond, G. K. (2012). U.S. Patent No. 8,224,613. Washington, DC: U.S. Patent and Trademark Office.
• [16] Desai, S. R., & Pickerd, J. J. (2014). U.S. Patent No. 8,650,010. Washington, DC: U.S. Patent and Trademark Office.
• [17] Takauchi, H., Tamura, H., Matsubara, S., Kibune, M., Doi, Y., Chiba, T., Anbutsu, H., Yamaguchi, H., Mori, T, Takatsu, M., Gotoh, K., Sakai T., & Yamamura T., (2003). A CMOS Multichannel 10Gb/s Transceiver. IEEE Journal of Solid-State Circuits, 38(12), 2094-2100. https://doi.org/10.1109/ISSCC.2003.1234212
• [18] B. Ham. (2004). Fibre channel - Methodologies for jitter and signal quality specification - MJSQ, Proceedings of InterNational Committee for Information Technology Standards (INCITS), 29-38.
• [19] Tektronix. (2002). Understanding and characterizing timing jitter [Application note].
• [20] Agilent. (2004). Analyzing Digital Jitter and its Components [Technical Note]. https://www.keysight.com/upload/cmc_upload/All/Analyzing_Digital_Jitter_and_its_Components.pdf
• [21] Li, Y., Bielby, S., Chowdhury, A., & Roberts, G. W. (2016). A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O. Journal of Electronic Testing, 32(4), 423-436. https://doi.org/10.1109/IMS3TW.2015.7177879
• [22] İspir, M., Özdil, Ö., & Yıldırım, A. (2013). Coloured noise generation with IFFT. IET Intelligent Signal Processing Conference 2013 (ISP 2013). UK. https://doi.org/10.1049/cp.2013.2062
• [23] Bidaj, K., Begueret, J. B., & Deroo, J. (2018). Jitter definition, measurement, generation, analysis, and decomposition. International Journal of Circuit Theory and Applications, 46(12), 2171-2188. https://doi.org/10.1002/cta.2559
• [24] Xia, T., Song, P., Jenkins, K. A., & Lo, J. C. (2004). Delay chain based programmable jitter generator. Proceedings of Ninth IEEE European Test Symposium (ETS 2004), France. https://doi.org/10.1109/ETSYM.2004.1347578
• [25] Jovanovic, G., Stojcev, M., Nikolic, T., & Stamenkovic, Z. (2012). Programmable jitter generator based on voltage-controlled delay line. Scientific Publications of the State University of Novi Pazar Series A: Applied Mathematics, Informatics and mechanics, 4(1), 61-73.
• [26] Jovanović, G., Stojčev, M., & Nikolić, T. (2013). Clock jitter generator with picoseconds resolution. International Journal of Electronics, 100(3), 779-792. https://doi.org/10.1080/00207217.2012.720953
• [27] Calbaza, D. E., & Savaria, Y. (1999). Jitter model of direct digital synthesis clock generators. IEEE International Symposium on Circuits and Systems (ISCAS), USA. https://doi.org/10.1109/ISCAS.1999.777791
• [28] Bidaj, K., Begueret, J. B., & Deroo, J. (2017). Generation of Colored Noise Patterns with Gaussian Jitter Distribution. IEEE Transactions on Instrumentation and Measurement, 66(7), 2576-2584. https://doi.org/10.1109/TIM.2017.2711738
• [29] Balestrieri, E., Picariello, F., Rapuano, S., & Tudosa, I. (2019). Review on jitter terminology and definitions. Measurement, 145, 264-273. https://doi.org/10.1016/j.measurement.2019.05.047
• [30] Cidon, I., Khamisy, A., & Sidi, M. (1994). Dispersed messages in discrete-time queues: delay, jitter and threshold crossing. Proceedings of INFOCOM’94 Conference on Computer Communications, Canada, 218-223. https://doi.org/10.1109/INFCOM.1994.337614
• [31] Ameri, A., & Roberts, G. W. (2011). Time-mode reconstruction iir filters for Σ∆ phase modulation applications, Edition of the Great Lakes Symposium on VLSI. Proceedings of the 21st edition of the Great Lakes symposium on VLSI, Switzerland, 423-426. https://doi.org/10.1145/1973009.1973099
• [32] Li, M., Peng, H. M., & Liao, C. S. (2000). Fast computation of time deviation and modified Allan deviation for telecommunications clock stability characterization. Proceedings of International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN 2000, USA, 156-160. https://doi.org/10.1109/ISPAN.2000.900280
• [33] Schnecker, M. (2012). Jitter Measurements in Serial Data Signals [White paper]. LeCroy Corporation. http://cdn.teledynelecroy.com/files/whitepapers/wp_jittermeasurement_in_serialdatasignals.pdf
• [34] Zamek, I., & Zamek, S. (2005). Definitions of jitter measurement terms and relationships. IEEEInternational Conference on Test, USA. https://doi.org/10.1109/TEST.2005.1583959
• [35] Duan, Y., Wu, H., Shimanouchi, M., Li, M. P., & Chen, D. (2018). A Low-Cost Comparator-Based Method for Accurate Decomposition of Deterministic Jitter in High-Speed Links. IEEE Transactions on Electromagnetic Compatibility, 61(2), 521-531. https://doi.org/10.1109/TEMC.2018.2821680
• [36] Marcu, M., Durbha, S., & Gupta, S. (2008). Duty-cycle distortion and specifications for jitter test-signal generation. Proceedings of IEEE International Symposium on Electromagnetic Compatibility, USA. https://doi.org/10.1109/ISEMC.2008.4652150
• [37] Liang, T., Fu, Z., Liu, H., Liu, K., & Xiao, Y. (2019). Minimizing the Jitter of Duty Cycle Distortion Correction Technology Based on Cross Point Eye Diagram Correction. IEEE Access, 7, 106238-106247. https://doi.org/10.1109/ACCESS.2019.2931474
• [38] Fu, Z., Liu, H., & Ren, N. (2018). Methodology for digital synthesis of ultra-narrow pulses. Electronics Letters, 54(16), 969-970. https://doi.org/10.1049/el.2018.1218
• [39] Ren, N., Fu, Z., Lei, S., Liu, H., & Tian, S. (2019). Methodology for Digital Synthesis of Deterministic and Random Jitter Generation on Rising or Falling Edges of Data Pattern. Electronics, 8(12), 1510-1525. https://doi.org/10.3390/electronics8121510
• [40] Keysight Technologies. (2017). Keysight N4963A Clock Synthesizer 13.5 GHz [User’s Guide]. http://literature.cdn.keysight.com/litweb/pdf/N4963-91021.pdf
• [41] SHF Communication Technologies AG. (2017). Creating Complex Jittered Test Patterns [Application Note]. https://www.shfcommunication.com/wp-content/uploads/appnotes/shf_app_note_jitter_with_awg.pdf

Uwagi

Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2021).