Proposal of a new structure for netfpga cards

• Autorzy: Michalski M. , Sielach T.
• Języki publikacji: EN

Abstrakty

EN

In this paper, we present a proposal of a new internal structure for NetFPGA cards and its analysis. We propose to use a switching fabric instead of a single pipeline. Such a change complicates some modules and connects several of them into a single, more complicated module. Their functionality is the same,but the delay of the server Ethernet frame will be decreased.

Słowa kluczowe

EN

NetFPGA; network switches models; FPGA

• Wydawca: Instytut Telekomunikacji i Informatyki Uniwersytetu Technologiczno-Przyrodniczego w Bydgoszczy
• Czasopismo: Image Processing & Communications
• Rocznik: 2017
• Tom: Vol. 22, no. 1
• Strony: 27--33
• Opis fizyczny: Bibliogr. 24 poz., rys., tab.

Twórcy

autor

Michalski M.

• Poznan University of Technology, Faculty of Electronics and Telecommunications, Polanka 3, 60-965 Poznan, Poland

autor

Sielach T.

• Poznan University of Technology, Faculty of Electronics and Telecommunications, Polanka 3, 60-965 Poznan, Poland

Bibliografia

• [1] Website of community and NetFPGA project: http://www.netfpga.org.
• [2] GibbG., LockwoodJ.W., NaousJ., HartkeP., McKeown N. (2008, August). NetFPGA: An Open Platform for Teaching How to Build Gigabit-rate Network Switches and Routers. In IEEE Transactions on Education, Volume: 51, Issue: 3 pp. 364-369.
• [3] Zilberman N., Audzevich Y., Covington G.A., Moore A.W. (2014, September). NetFPGA SUME: Toward 100 Gbps as Research Commodity, IEEE Micro, vol.34, no. 5, pp. 32-41.
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• [5] Xilinx ISE 10.1 Quick Start Tutorial.www.xilinx. com/itp/xilinx10/books/docs/qst/qst.pdf.
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• [8] ISE In-Depth. http://xilinx.com/direct/ ise10\_tutorials/ise10tut.pdf.
• [9] Kabacinski W., Michalski M. (2005, May). Widesense Nonblocking Log2(N,0,p) Switching Networks with Even Number of Stages. In Proc. IEEE ICC 2005, Seoul, South Korea.
• [10] Kabacinski W., Michalski M. (2006, December). TheRouting Algorithm and Wide-Sense Nonblocking Conditions for Multiplane Baseline Switching Networks. In IEEE Journal on Selected Areas in Communications, vol. 24, no. 12, pp. 35–44.
• [11] Danilewicz G., Kabaci´nski W., Zal M., Michalski M. (2008, April). A New Control Algorithm for Wide-sense Nonblocking Multiplane Photonic Banyan-type Switching Fabrics with Zero Crosstalk", In IEEE Journal on Selected Areas in Communications vol 26, no. 3, part 2, pp. 54–64.
• [12] Kabacinski W., Kleban J., Michalski M., Zal M., Pattavina A., Maier G. (2009, June). Rearranging Algorithms for Log2(N,0,p) Switching Networks with Even Number of Stages. International Workshop on High Performance Switching and Routing, Paris, France.
• [13] KabacinskiW., MichalskiM.(2011, June).TheAlgorithm for Rearrangements in the Log2(N,0,p) Fabrics with Odd Number of Stages.In IEEE International Conference on Communications ICC2011, Kyoto, Japan.
• [14] Kabacinski W., Michalski M. (2010, June). The FPGA Implementation of the Log2(N,0,p) Switching Fabric Control Algorithm. In IEEE International Conference on High Performance Switching and Routing, Dallas, TX, USA.
• [15] Kabacinski W., Michalski M. (2011, July). The FPGA Controller for the Rearrangeable Log2(N,0,p) Fabrics with an Even Number of Stages. In IEEE International Conference on High Performance Switching and Routing, HPSR 2011, Cartagena, Spain.
• [16] Kabacinski W., Michalski M. (2013, June). The Control Algorithm and the FPGA Controller for Non-interruptive Rearrangeable Log2(N,0,p) Switching Networks. In IEEE International Conference on Communications, ICC2013, Budapest, Hungary.
• [17] Michalski M. (2012, July). The Configurations for Experimental Study of the Network Performance. In 8th IEEE, IET International Symposium on Communication Systems, Networks and Digital Signal Processing (CSNDSP 2012).
• [18] Michalski M. (2009, April). A Software and Hardware System for a Fully Functional Remote Access to Laboratory Networks". In The Fifth International Conference on Networking and Services, Valencia, Spain, pp 561-565.
• [19] Michalski M. (2012, July). The Configurations for Experimental Study of the Network Performance. In 8th IEEE,IET International Symposium on Communication Systems, Networks and Digital Signal Processing (CSNDSP 2012).
• [20] Michalski M. (2014, July). The System for Delay Measurement in Ethernet Networks on NetFPGA Cards, In IEEE International Conference on High Performance Switching and Routing 2014, Vancouver, Canada.
• [21] Spirent Test Center.http://www.spirent.com/Products/Spirent-TestCenter/ Enterprise And Data Center Networks.
• [22] JDSU - MTS5800 traffic generator and analyzer. http://www.amt.pl/produkty/ telekomunikacja/sieci-dostepowe/296.html.
• [23] Oficial website of AM Technologies Company. http://www.amt.pl.
• [24] Xilinx University Program. http://xilinx.com/ support/university.html.

Uwagi

PL

Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę (zadania 2017).