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Abstrakty
An analogue median filter, realised in a 0.35 μm CMOS technology, is presented in this paper. The key advantages of the filter are: high speed of image processing (50 frames per second), low-power operation (below 1.25 mW under 3.3 V supply) and relatively high accuracy of signal processing. The presented filter is a part of an integrated circuit for image processing (a vision chip), containing: a photo-sensor matrix, a set of analogue pre-processors, and interface circuits. The analysis of the main parameters of the considered median filter is presented. The discussion of important limitations in the operation of the filter due to the restrictions imposed by CMOS technology is also presented.
Słowa kluczowe
Rocznik
Tom
Strony
725--730
Opis fizyczny
Bibliogr. 25 poz., wykr., rys., fot., tab.
Twórcy
autor
- Department of Microelectronic Systems, Gdańsk University of Technology, 11/12 Narutowicza St., 80-952 Gdańsk, Poland
autor
- Department of Microelectronic Systems, Gdańsk University of Technology, 11/12 Narutowicza St., 80-952 Gdańsk, Poland
autor
- Department of Microelectronic Systems, Gdańsk University of Technology, 11/12 Narutowicza St., 80-952 Gdańsk, Poland
autor
- Department of Microelectronic Systems, Gdańsk University of Technology, 11/12 Narutowicza St., 80-952 Gdańsk, Poland
Bibliografia
- [1] R. Tadeusiewicz and P. Korohoda, Computer Analysis andSignal Processing, Telecommunication Progress Publishing House, Cracow, 1997, (in Polish).
- [2] Y.-C. Hung, S.-H. Shieh, and C.-K. Tung, “A real-time currentmode CMOS analog median filtering cell for system-on-chip applications”, IEEE Conf. on Electron Devices and Solid-StateCircuits (EDSSC) 1, 361-364 (2007).
- [3] S. Siskos, “Low voltage analog median filters implementation”, IEEE Int. Conf. on Imaging Systems and Techniques (IST) 1, 166-170 (2010).
- [4] A. D´ıaz-S´anchez, J. Ram´ırez-Angulo, A. Lopez-Martin, and E. S´anchez-Sinencio, “A fully parallel CMOS analog median filter”, IEEE Trans. Circuits and Systems-II 51 (3), 116-123 (2004).
- [5] C.-Y. Huang, W.-H. Wei, and B.-D. Liu, “Design of a 1.5 V analog current-mode median filter”, Intelligent Sensors, SensorNetworks and Information Processing Conf. 1, 211-215 (2004).
- [6] G. Fikos, S. Vlassis, and S. Siskos “High-speed, accurate analogue CMOS rank filter”, Electronics Letters 36 (7), 593-594 (2000).
- [7] S. Vlassis and S. Siskos, “Precision multi-input current comparator and its application to analog median filter implementation”, Analog Integrated Circuits and Signal Processing 34 (3), 233-245 (2003).
- [8] N. Chartchai, N. Jintana, K. Boonying, C. Sorawat, and D. Kobchai, “A CMOS median filter circuit design”, Int. Symp.on Communications and Information Technologies (ISCIT ’06) 1, 1089-1092 (2006).
- [9] S. Vlassis and S. Siskos, “CMOS analogue median circuit”, Electronics Letters 35 (13), 1038-1040 (1999).
- [10] Y.-C. Hung and B.-D. Liu, “A 1.2-V rail-to-rail analog CMOS rank filter”, Int. Analog VLSI Workshop 1, 129-134 (1999).
- [11] I.E. Opris and G.T.A. Kovacs, “A high-speed median circuit”, IEEE J. Solid-State Circuits 32 (6), 905-908 (1997).
- [12] I. Opris and G. Kovacs, “Improved analogue median filter”, Electronics Letters 30 (4), 284-285 (1994).
- [13] P.H. Dietz and L.R. Carley, “An analog technology for finding the median”, IEEE Custom Integrated Circuits Conf. 1, 611-614 (1993).
- [14] J.S. Jimmy Li and W. Harvey Holmes, “Analog implementation of median filters for red-time signal processing”, IEEETrans. Circuits and Systems 35 (8), 1032-1033 (1988).
- [15] J.P. Fitch, E.J. Coyle, and N.C. Gallagher, “The analog median filter”, IEEE Trans. Circuits and Systems 33 (1), 94-102 (1986).
- [16] S.A Fahmy, P.Y.K Cheung, and W. Luk, ”High-throughput onedimensional median and weighted median filters on FPGA”, IET Computers & Digital Techniques 1, 384-394 (2009).
- [17] D. Richards, “VLSI median filters”, IEEE Trans. Acoustic,Speech, Signal Processing 38, 145-153 (1990).
- [18] C.-T. Chen, L.-G. Chen, and J.-H. Hsiao, “VLSI Implementation of a selective median filter”, IEEE Trans. on ConsumerElectronics 42 (1), 36-42 (1996).
- [19] H. Yamasaki and T. Shibata, “A real-time image-featureextraction and vector-generation VLSI employing arrayedshift- register architecture”, IEEE J. Solid-State Circ. 42 (9), 2046-2053 (2007).
- [20] W. Jendernalik, J. Jakusz, G. Blakiewicz, R. Piotrowski, and S. Szczepański, “CMOS realization of analogue processor for early vision processing”, Bull. Pol. Ac.: Tech. 59 (2), 141-147 (2011).
- [21] W. Jendernalik, J. Jakusz, G. Blakiewicz, and R. Piotrowski, “CMOS realization of special analogue processor supporting early vision processing”, IX Natl. Electronics Conf. KKE’2010 1, CD-ROM (2010), (in Polish).
- [22] W. Jendernalik, G. Blakiewicz, J. Jakusz, S. Szczepański, and R. Piotrowski, “An analog sub-miliwatt CMOS image sensor with pixel-lewel convolution processing”, IEEE Trans. Circuitsand Systems-I 60 (2), 279-289 (2013).
- [23] K.R. Laker and W.M.C. Sansen, Design of Analog IntegratedCircuits and Systems, McGraw-Hill, London, 1994.
- [24] M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G Welbers, “Matching properties of MOS transistors”, IEEE J. Solid-StateCirc. 24 (5), 1433-1439 (1989).
- [25] A.E. Gamal and H. Eltoukhy, “CMOS image sensors”, IEEECircuits & Devices Magazine 3, 6-20 (2005).
Typ dokumentu
Bibliografia
Identyfikator YADDA
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