Feasibility of FPGA to HPC computation migration of plasma impurities diagnostic algorithms

• Autorzy: Linczuk P. , Krawczyk R. D. , Zabolotny W. , Wojenski A. , Kolasinski P. , Pozniak K. T. , Kasprowicz G. , Chernyshova M. , Czarski T.

Identyfikatory

DOI

10.1515/eletel-2017-0043

• Języki publikacji: EN

Abstrakty

EN

We present a feasibility study of fast events parameters estimation algorithms regarding their execution time. It is the first stage of procedure used on data gathered from gas electron multiplier (GEM) detector for diagnostic of plasma impurities. Measured execution times are estimates of achievable times for future and more complex algorithms. The work covers usage of Intel Xeon and Intel Xeon Phi - high-performance computing (HPC) devices as a possible replacement for FPGA with highlighted advantages and disadvantages. Results show that less than 10 ms feedback loop can be obtained with the usage of 25% hardware resources in Intel Xeon or 10% resources in Intel Xeon Phi which leaves space for future increase of algorithms complexity. Moreover, this work contains a simplified overview of basic problems in actual measurement systems for diagnostic of plasma impurities, and emerging trends in developed solutions.

Słowa kluczowe

EN

plasma diagnostic; GEM system; feedback loops; Intel Xeon; Intel Xeon Phi; high performance computing HPC

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2017
• Tom: Vol. 63, No. 3
• Strony: 323--328
• Opis fizyczny: Bibliogr. 14 poz., tab., wykr.

Twórcy

autor

Linczuk P.

• University of Technology, Institute of Electronic System, Warsaw, Poland
• Institute of Plasma Physics and Laser Microfusion, Warsaw, Poland

autor

Krawczyk R. D.

• University of Technology, Institute of Electronic System, Warsaw, Poland

autor

Zabolotny W.

• University of Technology, Institute of Electronic System, Warsaw, Poland

autor

Wojenski A.

• University of Technology, Institute of Electronic System, Warsaw, Poland

autor

Kolasinski P.

• University of Technology, Institute of Electronic System, Warsaw, Poland

autor

Pozniak K. T.

• University of Technology, Institute of Electronic System, Warsaw, Poland

autor

Kasprowicz G.

• University of Technology, Institute of Electronic System, Warsaw, Poland

autor

Chernyshova M.

• Institute of Plasma Physics and Laser Microfusion, Warsaw, Poland

autor

Czarski T.

• Institute of Plasma Physics and Laser Microfusion, Warsaw, Poland

Bibliografia

• [1] B. Plumer, “Have we hit ”the end of the fossil fuel era”? Not even close.” http://www.vox.com/2015/12/14/10121638/fossil-fueldominance, 2015.
• [2] “The End Of Fossil Fuels,” https://www.ecotricity.co.uk/our-greenenergy/energy-independence/the-end-of-fossil-fuels.
• [3] P. Linczuk, R. D. Krawczyk, K. T. Pozniak, G. Kasprowicz, A. Wojenski, M. Chernyshova, and T. Czarski, “Algorithm for fast event parameters estimation on GEM acquired data,” SPIE, vol. 10013, 2016.
• [4] A. Wojenski, K. T. Pozniak, G. Kasprowicz, P. Kolasinski, R. Krawczyk, W. Zabolotny, M. Chernyshova, T. Czarski, and K. Malinowski, “Fpga-based gem detector signal acquisition for sxr spectroscopy system,” Journal of Instrumentation, vol. 11, no. 11, p. C11035, 2016. [Online]. Available: http://stacks.iop.org/1748-0221/11/i=11/a=C11035
• [5] T. Czarski, M. Chernyshova, K. Malinowski, K. T. Pozniak, G. Kasprowicz, P. Kolasinski, R. Krawczyk, A. Wojenski, and W. Zabolotny, “The cluster charge identification in the gem detector for fusion plasma imaging by soft x-ray diagnostics,” Review of Scientific Instruments, vol. 87, no. 11, p. 11E336, 2016. [Online]. Available: http://aip.scitation.org/doi/abs/10.1063/1.4961559
• [6] T. Czarski, K. T. Pozniak, M. Chernyshova, K. Malinowski, G. Kasprowicz, P. Kolasinski, R. Krawczyk, A. Wojenski, and W. Zabolotny, “On line separation of overlapped signals from multi-time photons for the GEM based detection system,” SPIE, vol. 9662, 2015.
• [7] “Xeon Phi 7250 KNL generation processor,” http://ark.intel.com/products/94035/Intel-Xeon-Phi-Processor-7250-16GB-1_40-GHz-68-core.
• [8] J. Lawley, “Understanding Performance of PCI Express Systems,” http://www.xilinx.com/support/documentation/white papers/wp350.pdf.
• [9] L. Rota, M. Caselle, S. Chilingaryan, A. Kopmann, and M. Weber, “A pcie dma architecture for multi-gigabyte per second data transmission,” IEEE Transactions on Nuclear Science, vol. 62, no. 3, pp. 972–976, June 2015.
• [10] “Intel Xeon Processor E5-2630 v3,” http://ark.intel.com/products/83356/Intel-Xeon-Processor-E5-2630-v3-20M-Cache-2 40-GHz.
• [11] “Intel Xeon Phi Coprocessor 31S1P,” http://ark.intel.com/products/79539/Intel-Xeon-Phi-Coprocessor-31S1P-8GB-1_100-GHz-57-core.
• [12] “Intel Server Board S2600CW Family,” http://www.intel.com/content/www/us/en/motherboards/server-motherboards/server-boards2600cw.html.
• [13] “OpenMP* Thread Affinity Control,” https://software.intel.com/en-us/articles/openmp-thread-affinity-control.
• [14] “Intel Dual-Socket Server Boards,” http://ark.intel.com/products/family/43716/Dual-Socket-Server-Boards.

Uwagi

PL

Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę (zadania 2017).