Bit Error Rate Tester for 10 Gb/s Fibre Optic Link

• Autorzy: Śliwczyński Ł. , Krehlik P.
• Języki publikacji: EN

Abstrakty

EN

The bit error rate tester suitable for operation in 10 Gb/s fibre optic links is described in the paper. The BER tester was built from commercially available components. Generation and reception of 10 Gb/s data stream is performed with help of high-speed serialiser and deserialiser by Maxim. The main functions of the BER tester are implemented in the field programmable gate array (FPGA) Spartan3 device by Xilinx. The part of the FPGA runs with the clock speed equal to 622 MHz. Some measurement results obtained in the fibre optic links operated with 10 Gb/ data rate are also presented.

Słowa kluczowe

EN

bit error rate; fibre optic links; field programmable gate array (FPGA)

• Wydawca: Publishing House of Poznan University of Technology
• Czasopismo: Advances in Electronics and Telecommunications
• Rocznik: 2010
• Tom: Vol. 1, no. 2
• Strony: 70--73
• Opis fizyczny: Bibliogr. 8 poz., rys.

Twórcy

autor

Śliwczyński Ł.

• AGH University of Science and Technology, Mickiewicza 30 Ave., 30-059 Krakow, Poland

autor

Krehlik P.

• AGH University of Science and Technology, Mickiewicza 30 Ave., 30-059 Krakow,

Bibliografia

• [1] “BERTScope S,” [online], http://www.bertscope.com.
• [2] “ParBERT,” [online], http://www.agilent.com.
• [3] “J-BERT N4903A,” [online], http://www.agilent.com.
• [4] C. Coombs, Electronic Instrument Handbook. McGraw-Hill, 1995.
• [5] “ITU-T Recommendations O151, O152 and O153,” Tech. Rep.
• [6] A. Liwak and L. Śliwczyński, “Laboratoryjny miernik bitowej stopy błędu,” in Proc. of Poznańskie Warsztaty Telekomunikacyjne, 2004, pp. 75–80, (in Polish).
• [7] L. Śliwczyński, “PRBS generator runs at 1.5 Gbps,” in Proc. of EDN, Mar. 2007, pp. 76–80.
• [8] PicoBlaze 8-bit Embedded Microcontroller User Guide for Spartan-3, Virtex-II, and Virtex-II Pro FPGAs, Xilinx, 2005.