Identyfikatory
Warianty tytułu
Języki publikacji
Abstrakty
The Vertical Slit-based Field-Effect Transistor (VeSFET) is a novel junctionless device with two identical, independently controlled gates. The VeSFET, so far prototyped only as single-device test structures, has been considered in the literature exclusively as a component of digital systems. This article shows that the device’s properties make it attractive also for the analog designer. Some of the VeSFET’s analog-design related parameters are compared with those of the MOSFET of the corresponding technology node. Subsequently, a two-stage Miller operational transconductance amplifier (OTA) is proposed that makes use of the VeSFET’s two independently-controlled gates to drastically reduce the common-mode gain. An example application of the OTA in a current mirror is also presented.
Słowa kluczowe
Rocznik
Tom
Strony
79--86
Opis fizyczny
Bibliogr. 15 poz.
Twórcy
autor
- Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Warsaw, Poland
autor
- Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Warsaw, Poland
Bibliografia
- [1] W. Maly, “Integrated Circuit, Device, System, and Method of Fabrication”, Patent Application WO 2007/133775 A2, 2007.
- [2] W. Maly et al., “Twin Gate, Vertical Slit FET (VeSFET) for Highly Periodic Layout and 3D Integration,” Proc. 18th Intl. Conf. Mixed Design of Integrated Circuits and Systems MIXDES 2011 , Gliwice, Poland, 16– 18 June 2011, pp. 145–150.
- [3] http://vestics.org
- [4] P. Freitas, G. Billiot, H. Lapuyade, J.B. Begueret, “Analog Design Considerations For Independently Driven Double Gate MOSFETs and Their Application in a Low-Voltage OTA,” Proc. 14th IEEE Intl. Conf. on Electronics, Circuits and Systems ICECS 2007 , 11–14 Dec. 2007, pp. 198–201.
- [5] A. Pfitzner, “Vertical-Slit Field-Effect Transistor (VeSFET) – Design Space Exploration and DC Model,” Proc. 18th Intl. Conf. Mixed Design of Integrated Circuits and Systems MIXDES 2011 , Gliwice, Poland, 16– 18 June 2011, pp. 151–156.
- [6] A. Kamath et al., “Realizing AND and OR Functions With Single Vertical-Slit Field-Effect Transistor,” IEEE Electron Device Letters, Vol. 33, No. 2, pp. 152–154, Feb. 2012.
- [7] M. Weis et al., “Adder Circuits with Transistors Using Independently Controlled Gates,” Proc. IEEE Intl. Symposium on Circuits and Systems ISCAS 2009 , pp. 449–452.
- [8] Y.-W. Lin, M. Marek-Sadowska, W. P. Maly, “On Cell Layout - Performance Relationships in VeSFET-Based, High-Density Regular Circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, No. 2, Feb. 2011, pp. 229–241.
- [9] X. Qiu; M. Marek-Sadowska, W. Maly, “Vertical Slit Field Effect Tran- sistor in Ultra-Low Power Applications,” Proc. 13th Intl. Symposium on Quality Electronic Design (ISQED) , 19–21 March 2012, pp. 384–390.
- [10] D. Kasprowicz, B. Swacha, “VeSFET as an Analog-Circuit Component,” Proc. IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2013 , Karlovy Vary, Czech Republic, 8–10 April 2013, pp. 199–204.
- [11] Sentaurus Device, Synopsys, Inc., Dec. 2010, Version E-2010.12.
- [12] HSPICE, Synopsys, Inc., Dec. 2010, Version E-2010.12.
- [13] http://ptm.asu.edu/modelcard/2006/90nm bulk.pm
- [14] D. Foty, D. Binkley, M. Bucher, “Starting Over: gm/Id-Based MOSFET Modeling as a Basis for Modernized Analog Design Methodologies”, Technical Proc. 2002 Intl. Conf. on Modeling and Simulation of Microsystems , Vol. 1, pp. 682–685.
- [15] D. Kasprowicz, “A compact model of VeSFET capacitances,” Proc. 18th Intl. Conf. Mixed Design of Integrated Circuits and Systems MIXDES 2011 , Gliwice, Poland, 16–18 June 2011, pp. 121–126.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-df42bca7-9cd8-4dde-a072-ffd12d955f3d