A Qucs/QucsStudio swept parameter technique for statistical circuit simulation

• Autorzy: Brinson M. E.
• Języki publikacji: EN

Abstrakty

EN

Qucs and QucsStudio open source circuit simulators have a wealth of built in swept data features, including facilities for linear and logarithmic scans of simulation variables and for setting component values and device parameters. These simulators also allow semicolon separated lists of numerical values to be used as swept data. This little known feature provides a very flexible mechanism for generating component and device parameter statistical data. An outline of a statistical circuit simulation technique is presented in this paper. The proposed technique can be used with any general purpose circuit simulator equipped with swept data capabilities and as such is suitable for the study of device and circuit performance resulting from variations in device parameters and component values. The operation of the proposed simulation technique is illustrated with the results from an investigation of the statistical performance of a simple MOS current mirror integrated circuit cell, modeled with a speed optimized Verilog-A version of a long channel EPFL_EKV v2.6 MOS transistor model.

Słowa kluczowe

EN

QucsStudio; Qucs; statistical circuit simulation; swept parameter lists; Verilog-A compact semiconductor device models

PL

QucsStudio; Qucs; statystyczna symulacja obwodu; Verilog-A

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2013
• Tom: Vol. 4, nr 3
• Strony: 92--97
• Opis fizyczny: Bibliogr. 17 poz.

Twórcy

autor

Brinson M. E.

• Centre for Communications Technology Research, London Metropolitan University, Holloway, London, UK

Bibliografia

• [1] G. J. Coram, “How to (and how not to) write a compact model in Verilog- A”, IEEE International Behavioural Modeling and Simulation Conference (BMAS 2004), San Jose, CA, USA. 2004, 97-106.
• [2] M. Margraf, S. Jahn, J. Flucke, R. Jacob, V. Habchi, T. Ishikawa, A. Gopala Krishna, M. Brinson, H. Parruitte, B. Roucaries , G. Kraut and F. Schreuder. Qucs (Quite universal circuit simulator), Version 0.0.17, http://qucs.sourceforge.net/index.html, 2013. [accessed January 2013].
• [3] M. Margraf, QucsStudio, Version 1.4.3. http://www.mydarc.de/DD6UM/QucsStudio/qucsstudio.html, 2013. [accessed January 2013].
• [4] P. Nenzi, ngspice release 25, http://ngspice.sourceforge.net/index.html, 2013. [accessed January 2013].
• [5] A. Davis, Gnucap, Version 0.35, http://www.gnu.org/software/gnucap/, 2009. [accessed January 2013].
• [6] A. R. Newton, D. O. Pederson, A. Sangiovamai-Vincentelli, “A SPICE 2g User’s Guide”, Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, 1981.
• [7] B. Johnson, T. Quarles, A. R. Newton, D. O. Pederson, A. Sangiovanni-Vincentelli,”A SPICE3 Version 3f User’s Manual”, Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, 1992.
• [8] Accellera “Verilog-AMS Language Reference Manual, Version 2.2”, 2004, http//www.accellera.org. 2010. [accessed January 2013].
• [9] L. Lemaitre, G. J. Corum, C. McAndrew and K Kundert, “Extensions to Verilog-A to support compact device modeling”, Proceedings of the IEEE International Workshop on Behavioural Modeling and Simulation, BMAS, 7-8 Oct. 2003, pp, 134-138.
• [10] Yogesh Chauhan, “Transitioning BSHVI4 to BSHVI6”, University of California, Berkeley, CA, http://www.mos-ak.org/india/presentations/Chauhan_BSIM6_MOS-AK_India12.pdf.
• [11] Compact Model Council, TechAmerica, Arlington, VA. http://www.geia.org , 2009. [accessed January 2013].
• [12] Cadence, “PSpice A/D and Advanced Analysis”, http://www.cadence.com/products/orcad/pspice_simulation/pages/default.aspx, 2013. [accessed January 2013].
• [13] M. Bucher et al., “The EPFL-EKV MOSFET V2.6 model equations for simulation”, Technical Report. Electronics Laboratories, Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland, June 1997.
• [14] GNU Octave. 1992-2013, Available from: http://www.gnu.org/software/octave/.
• [15] QucsStudio, Version 1.4.3. Help file: section — Description of Qucs file formats. http://www.mydarc.de/DD6UM/QucsStudio/qucsstudio.html, 2013. [accessed January 2013].
• [16] M.E. Brinson ands. Jahn, “Compact device modeling for established and emerging technologies with the Qucs GPL circuit simulator”, MIXDES 2009, 16 International Conference, Mixed Design and Integrated Circuits, Lodz, June 25-27,2009.
• [17] S. Jahn, M. Brinson, H. Parruitte, B. Ardouin, P. Nenzi and L. Lemaitre, ”GNU simulators supporting Verilog-A compact model standardization“, MOS-AK meeting, Premstaetten 2007, http://www.mosak.org/premstaetten/papers/MOSAK QUCS ngspice_ADMS.pdf, [accessed July 2012].