Implementing SHA-3 candidate BLAKE algorithm in Field Programmable Gate Arrays

• Autorzy: Sugier J.
• Języki publikacji: EN

Abstrakty

EN

BLAKE is a cryptographic hash function proposed as a candidate in SHA-3 contest where he successfully qualified to the final round with other 4 candidates. Although it eventually lost to KECCAK it is still considered as a suitable solution with good cryptographic strength and great performance especially in software realizations. For these advantages BLAKE is commonly selected to be a hash function of choice in many contemporary IT systems in applications like digital signatures or message authentication. The purpose of this paper is to evaluate how the algorithm is suitable to be implemented in hardware using low-cost Field Programmable Gate Array (FPGA) devices, particularly to test how efficiently its complex internal transformations can be realized with FPGA resources when overall size of the implementation grows substantially with multiple rounds of the cipher running in parallel in hardware and capacity of the configurable array is used up to its limits. The study was made using the set of 7 different architectures with different loop unrolling factors and with optional application of pipelining, with each architecture being implemented in two popular families of FPGA devices from Xilinx. Investigation of the internal characteristic of the implementations generated by the tools helped in analysis how the fundamental mechanism of loop unrolling with or without pipelining works in case of this particular cipher.

Słowa kluczowe

EN

BLAKE algorithm; FPGA; hash function; implementation efficiency; loop unrolling; pipelining

• Wydawca: Polskie Towarzystwo Bezpieczeństwa i Niezawodności
• Czasopismo: Journal of Polish Safety and Reliability Association
• Rocznik: 2016
• Tom: Vol. 7, No. 1
• Strony: 193--200
• Opis fizyczny: Bibliogr. 12 poz., rys., tab., wykr.

Twórcy

autor

Sugier J.

• University of Science and Technology, Wrocław, Poland

Bibliografia

• [1] Aumasson, J. P., Henzen, L., Meier, W. et al. (2010) SHA-3 proposal BLAKE, version 1.3, [available at: https://www.131002.net/blake/ blake.pdf; retrieved March 2016].
• [2] Bernstein, D. J. (2008). The Salsa20 family of stream ciphers. New Stream Cipher Designs. Springer, 84-97.
• [3] ECRYPT II Project (2012). SHA-3 Hardware Implementations, [available at: http://ehash.iaik. tugraz.at/wiki/SHA-3_Hardware_ Implementations; retrieved March 2016].
• [4] Gaj, K., Homsirikamol, E., Rogawski, M. et al. (2012). Comprehensive evaluation of high-speed and medium-speed implementations of five SHA3 finalists using Xilinx and Altera FPGAs. The Third SHA-3 Candidate Conference, Washington, DC, USA.
• [5] Gaj, K., Southern, G., & Bachimanchi, R. (2007). Comparison of hardware performance of selected Phase II eSTREAM candidates. Proc. State of the Art of Stream Ciphers Workshop, eSTREAM, ECRYPT Stream Cipher Project, Report. 26, 2007.
• [6] Junkg, B. & Apfelbeck, J. (2011). Area-efficient FPGA implementations of the SHA-3 finalists. 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 235-241.
• [7] Sugier, J. (2013). Low-cost hardware implementations of Salsa20 stream cipher in programmable devices. Journal of Polish Safety and Reliability Association, Summer Safety and Reliability Seminars 4, 1, 121-128.
• [8] Sugier, J. (2014). Low cost FPGA devices in high speed implementations of Keccak-f hash algorithm. Advances in Intelligent and Soft computing: New Results in Dependability and Complex Systems. Proc. 9th Int. Conf. Dependability and Complex Systems DepCoSRELCOMEX, Springer 286, 433-442.
• [9] Tillich, S., Feldhofer, M., Issovits, W., et al. (2009). Compact hardware implementations of the SHA-3 candidates ARIRANG, BLAKE, Grøstl, and Skein. IACR Cryptology ePrint Archive, 349.
• [10] Xilinx, Inc. (2009). Spartan-3 Family Data Sheet, [available at: www.xilinx.com (ds099.pdf); retrieved March 2016].
• [11] Xilinx, Inc. (2011). Spartan-6 Family Overview. , [available at: www.xilinx.com (ds160.pdf); retrieved March 2016].
• [12] Yan, J., & Heys, H. M. (2007). Hardware implementation of the Salsa20 and Phelix stream ciphers. Proc. Canadian Conference on Electrical and Computer Engineering CCECE 2007. IEEE, 1125-1128.

Uwagi

Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę (zadania 2017).