On implementation of FFT processor in XILINX FPGA using high-level synthesis

• Autorzy: Smyk Robert , Czyżak Maciej

Identyfikatory

DOI

10.21008/j.1897-0737.2020.104.0002

• Języki publikacji: EN

Abstrakty

EN

The paper presents results of the high level synthesis of an 1024-point radix-2 FFT processors in Xilinx Vivado FPGA environment. The use of various directives controlling the synthesis process is examined. The results indicate that using the proper set of directives the latency of the processor can be reduced by 95% from about 35k for the default parameters to 1.5k cycles after optimizations.

Słowa kluczowe

EN

Fast Fourier Transform Processor; FPGA; high-level synthesis

• Wydawca: Wydawnictwo Politechniki Poznańskiej
• Czasopismo: Poznan University of Technology Academic Journals. Electrical Engineering
• Rocznik: 2020
• Tom: No. 104
• Strony: 17--33
• Opis fizyczny: Bibliogr. 54 poz., rys., tab.

Twórcy

autor

Smyk Robert

• Państwowa Wyższa Szkoła Zawodowa w Elblągu

autor

Czyżak Maciej

Bibliografia

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Uwagi

Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2020).